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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net
Subject: [Qemu-devel] [PATCH v2 0/8] TriCore add instructions of RR and RR1 opcode format
Date: Wed, 17 Dec 2014 15:59:13 +0000	[thread overview]
Message-ID: <1418831961-27658-1-git-send-email-kbastian@mail.uni-paderborn.de> (raw)

Hi,

here is the next patchset for the TriCore ISA, which steadily moves towards being a usable qemu guest.
This patchset first cleans up the SSOV/SUOV makros, which were only suitable for 32 bit arithmetic,
to make room for 16bit SSOV/SUOV arithmetic used for the RR insn. These are splitted into four patches,
seperated by the first opcode all insn of one patch have. I also added missed 1.6 insns and fixed some
minor errors. The last patch adds the first half of the RR1 insn.

Cheers,
Bastian

v1 -> v2:
    - SSOV32/SUOV32 are now regular functions.
    - gen_cond_w now uses neg and saves a temp.
    - SSOV16/SUOV16 are now regular functions.
    - Use TCG_CALL_NO_RWG_SE for all helpers not using globals.
    - Use more compact code for helper_parity. (Thanks Richard!)
    - Remove redundant temp creation.
    - mul_h/mulm_h/mulr_h: * move arg extraction to tcg.
                           * compute psw flags in tcg-op now.
                           * helper now use TCG_CALL_NO_RWG_SE flag.

Bastian Koppelmann (8):
  target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
  target-tricore: Add instructions of RR opcode format, that have 0xb as
    the first opcode
  target-tricore: Add instructions of RR opcode format, that have 0xf as
    the first opcode
  target-tricore: Add instructions of RR opcode format, that have 0x1 as
    the first opcode
  target-tricore: Add instructions of RR opcode format, that have 0x4b
    as the first opcode
  target-tricore: Add missing 1.6 insn of BOL opcode format
  target-tricore: Fix MFCR/MTCR insn and B format offset.
  target-tricore: Add instructions of RR1 opcode format, that have 0xb3
    as first opcode

 target-tricore/helper.h          |   59 +++
 target-tricore/op_helper.c       | 1086 +++++++++++++++++++++++++++++++++++---
 target-tricore/translate.c       |  992 +++++++++++++++++++++++++++++++++-
 target-tricore/tricore-opcodes.h |   14 +-
 4 files changed, 2069 insertions(+), 82 deletions(-)

--
2.1.3

             reply	other threads:[~2014-12-17 14:59 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-17 15:59 Bastian Koppelmann [this message]
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 Bastian Koppelmann
2014-12-17 15:42   ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode Bastian Koppelmann
2014-12-17 15:47   ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf " Bastian Koppelmann
2014-12-17 15:48   ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 " Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b " Bastian Koppelmann
2014-12-17 15:51   ` Richard Henderson
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset Bastian Koppelmann
2014-12-17 15:59 ` [Qemu-devel] [PATCH v2 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode Bastian Koppelmann
2014-12-17 16:08   ` Richard Henderson

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