From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48424) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1G4R-0002oU-Qt for qemu-devel@nongnu.org; Wed, 17 Dec 2014 09:59:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1G4K-00065o-Lo for qemu-devel@nongnu.org; Wed, 17 Dec 2014 09:59:23 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60558) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1G4K-00065M-FK for qemu-devel@nongnu.org; Wed, 17 Dec 2014 09:59:16 -0500 From: Bastian Koppelmann Date: Wed, 17 Dec 2014 15:59:13 +0000 Message-Id: <1418831961-27658-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v2 0/8] TriCore add instructions of RR and RR1 opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net Hi, here is the next patchset for the TriCore ISA, which steadily moves towards being a usable qemu guest. This patchset first cleans up the SSOV/SUOV makros, which were only suitable for 32 bit arithmetic, to make room for 16bit SSOV/SUOV arithmetic used for the RR insn. These are splitted into four patches, seperated by the first opcode all insn of one patch have. I also added missed 1.6 insns and fixed some minor errors. The last patch adds the first half of the RR1 insn. Cheers, Bastian v1 -> v2: - SSOV32/SUOV32 are now regular functions. - gen_cond_w now uses neg and saves a temp. - SSOV16/SUOV16 are now regular functions. - Use TCG_CALL_NO_RWG_SE for all helpers not using globals. - Use more compact code for helper_parity. (Thanks Richard!) - Remove redundant temp creation. - mul_h/mulm_h/mulr_h: * move arg extraction to tcg. * compute psw flags in tcg-op now. * helper now use TCG_CALL_NO_RWG_SE flag. Bastian Koppelmann (8): target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode target-tricore: Add missing 1.6 insn of BOL opcode format target-tricore: Fix MFCR/MTCR insn and B format offset. target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode target-tricore/helper.h | 59 +++ target-tricore/op_helper.c | 1086 +++++++++++++++++++++++++++++++++++--- target-tricore/translate.c | 992 +++++++++++++++++++++++++++++++++- target-tricore/tricore-opcodes.h | 14 +- 4 files changed, 2069 insertions(+), 82 deletions(-) -- 2.1.3