From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34583) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1e3y-0000Yn-NI for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1e3p-0006dI-J2 for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:30 -0500 From: Tom Musta Date: Thu, 18 Dec 2014 10:34:31 -0600 Message-Id: <1418920477-11669-4-git-send-email-tommusta@gmail.com> In-Reply-To: <1418920477-11669-1-git-send-email-tommusta@gmail.com> References: <1418920477-11669-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit. This is analogous to the other "available" bits in the MSR (FP, VSX, etc.). NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped with a PPC64 bit check. Signed-off-by: Tom Musta --- target-ppc/translate.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d381632..7217041 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -203,6 +203,7 @@ typedef struct DisasContext { int altivec_enabled; int vsx_enabled; int spe_enabled; + int tm_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint64_t insns_flags; @@ -11311,6 +11312,13 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, } else { ctx.vsx_enabled = 0; } +#if defined(TARGET_PPC64) + if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { + ctx.tm_enabled = msr_tm; + } else { + ctx.tm_enabled = 0; + } +#endif if ((env->flags & POWERPC_FLAG_SE) && msr_se) ctx.singlestep_enabled = CPU_SINGLE_STEP; else -- 1.7.1