From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y1e41-0000dT-98 for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y1e3r-0006fx-Ob for qemu-devel@nongnu.org; Thu, 18 Dec 2014 11:36:33 -0500 From: Tom Musta Date: Thu, 18 Dec 2014 10:34:33 -0600 Message-Id: <1418920477-11669-6-git-send-email-tommusta@gmail.com> In-Reply-To: <1418920477-11669-1-git-send-email-tommusta@gmail.com> References: <1418920477-11669-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Tom Musta , agraf@suse.de Define mnemonics for the various bit fields in the Transaction EXception And Summary Register (TEXASR). --- target-ppc/cpu.h | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 38176c0..91a03f6 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -558,6 +558,26 @@ struct ppc_slb_t { #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */ #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */ +/* Transaction EXception And Summary Register bits */ +#define TEXASR_FAILURE_PERSISTENT (63 - 7) +#define TEXASR_DISALLOWED (63 - 8) +#define TEXASR_NESTING_OVERFLOW (63 - 9) +#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) +#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) +#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) +#define TEXASR_TRANSACTION_CONFLICT (63 - 13) +#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) +#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) +#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) +#define TEXASR_ABORT (63 - 31) +#define TEXASR_SUSPENDED (63 - 32) +#define TEXASR_PRIVILEGE_HV (63 - 34) +#define TEXASR_PRIVILEGE_PR (63 - 35) +#define TEXASR_FAILURE_SUMMARY (63 - 36) +#define TEXASR_TFIAR_EXACT (63 - 37) +#define TEXASR_ROT (63 - 38) +#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ + enum { POWERPC_FLAG_NONE = 0x00000000, /* Flag for MSR bit 25 signification (VRE/SPE) */ -- 1.7.1