From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y2kbW-00067V-AA for qemu-devel@nongnu.org; Sun, 21 Dec 2014 12:47:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y2kbQ-0000gC-Jc for qemu-devel@nongnu.org; Sun, 21 Dec 2014 12:47:42 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:49360) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y2kbQ-0000fr-Cp for qemu-devel@nongnu.org; Sun, 21 Dec 2014 12:47:36 -0500 From: Bastian Koppelmann Date: Sun, 21 Dec 2014 18:47:36 +0000 Message-Id: <1419187669-13576-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 00/13] tricore patches List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alexander.zuepke@hs-rm.de, rth@twiddle.net The following changes since commit c4e7c17a8ecb41cdbb81374a128161c614ba1f1e: Merge remote-tracking branch 'remotes/kraxel/tags/pull-roms-20141217-1' into staging (2014-12-20 21:28:53 +0000) are available in the git repository at: https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20141221 for you to fetch changes up to 9655b9328a566116c198c52792775a0641d56915: target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode (2014-12-21 18:35:49 +0000) ---------------------------------------------------------------- TriCore RR, RR1 insn added and several bug fixes ---------------------------------------------------------------- Alex Zuepke (4): target-tricore: fix offset masking in BOL format target-tricore: typo in BOL format target-tricore: add missing 64-bit MOV in RLC format target-tricore: pretty-print register dump and show more status registers Bastian Koppelmann (9): target-tricore: Fix mask handling JNZ.T being 7 bit long target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode target-tricore: Add missing 1.6 insn of BOL opcode format target-tricore: Fix MFCR/MTCR insn and B format offset. target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode target-tricore/helper.h | 59 +++ target-tricore/op_helper.c | 1086 +++++++++++++++++++++++++++++++++++--- target-tricore/translate.c | 1034 +++++++++++++++++++++++++++++++++++- target-tricore/tricore-opcodes.h | 19 +- 4 files changed, 2104 insertions(+), 94 deletions(-) -- 2.2.1