From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alexander.zuepke@hs-rm.de, rth@twiddle.net
Subject: [Qemu-devel] [PULL 01/13] target-tricore: fix offset masking in BOL format
Date: Sun, 21 Dec 2014 18:47:37 +0000 [thread overview]
Message-ID: <1419187669-13576-2-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1419187669-13576-1-git-send-email-kbastian@mail.uni-paderborn.de>
From: Alex Zuepke <alexander.zuepke@hs-rm.de>
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/tricore-opcodes.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 0a9122c..70ac5ff 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -114,7 +114,7 @@
/* BOL Format */
#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
- (MASK_BITS_SHIFT(op, 22, 27) >> 10))
+ (MASK_BITS_SHIFT(op, 22, 27) << 10))
#define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
(MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
--
2.2.1
next prev parent reply other threads:[~2014-12-21 17:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-21 18:47 [Qemu-devel] [PULL 00/13] tricore patches Bastian Koppelmann
2014-12-21 18:47 ` Bastian Koppelmann [this message]
2014-12-21 18:47 ` [Qemu-devel] [PULL 02/13] target-tricore: typo in BOL format Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 04/13] target-tricore: pretty-print register dump and show more status registers Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being 7 bit long Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 06/13] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 07/13] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 08/13] target-tricore: Add instructions of RR opcode format, that have 0xf " Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 09/13] target-tricore: Add instructions of RR opcode format, that have 0x1 " Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 10/13] target-tricore: Add instructions of RR opcode format, that have 0x4b " Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 11/13] target-tricore: Add missing 1.6 insn of BOL opcode format Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 12/13] target-tricore: Fix MFCR/MTCR insn and B format offset Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 13/13] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode Bastian Koppelmann
2014-12-22 14:52 ` [Qemu-devel] [PULL 00/13] tricore patches Peter Maydell
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