From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53079) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y2kbZ-00067X-Qm for qemu-devel@nongnu.org; Sun, 21 Dec 2014 12:47:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y2kbQ-0000gM-Je for qemu-devel@nongnu.org; Sun, 21 Dec 2014 12:47:45 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:49371) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y2kbQ-0000fy-E0 for qemu-devel@nongnu.org; Sun, 21 Dec 2014 12:47:36 -0500 From: Bastian Koppelmann Date: Sun, 21 Dec 2014 18:47:39 +0000 Message-Id: <1419187669-13576-4-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1419187669-13576-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1419187669-13576-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alexander.zuepke@hs-rm.de, rth@twiddle.net From: Alex Zuepke Signed-off-by: Alex Zuepke Reviewed-by: Bastian Koppelmann Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 12 ++++++++++++ target-tricore/tricore-opcodes.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index c132223..e3eeedb 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, case OPC1_32_RLC_MOV: tcg_gen_movi_tl(cpu_gpr_d[r2], const16); break; + case OPC1_32_RLC_MOV_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + if ((r2 & 0x1) != 0) { + /* TODO: raise OPD trap */ + } + tcg_gen_movi_tl(cpu_gpr_d[r2], const16); + tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); + } else { + /* TODO: raise illegal opcode trap */ + } + break; case OPC1_32_RLC_MOV_U: const16 = MASK_OP_RLC_CONST16(ctx->opcode); tcg_gen_movi_tl(cpu_gpr_d[r2], const16); @@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_32_RLC_ADDIH_A: case OPC1_32_RLC_MFCR: case OPC1_32_RLC_MOV: + case OPC1_32_RLC_MOV_64: case OPC1_32_RLC_MOV_U: case OPC1_32_RLC_MOV_H: case OPC1_32_RLC_MOVH_A: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 7aa6aed..a76a7e4 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -487,6 +487,7 @@ enum { OPC1_32_RLC_ADDIH_A = 0x11, OPC1_32_RLC_MFCR = 0x4d, OPC1_32_RLC_MOV = 0x3b, + OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */ OPC1_32_RLC_MOV_U = 0xbb, OPC1_32_RLC_MOV_H = 0x7b, OPC1_32_RLC_MOVH_A = 0x91, -- 2.2.1