From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alexander.zuepke@hs-rm.de, rth@twiddle.net
Subject: [Qemu-devel] [PULL 04/13] target-tricore: pretty-print register dump and show more status registers
Date: Sun, 21 Dec 2014 18:47:40 +0000 [thread overview]
Message-ID: <1419187669-13576-5-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1419187669-13576-1-git-send-email-kbastian@mail.uni-paderborn.de>
From: Alex Zuepke <alexander.zuepke@hs-rm.de>
Now using psw_read() to retrieve the status bits correctly.
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index e3eeedb..3d87346 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -85,22 +85,31 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f,
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
+ uint32_t psw;
int i;
- cpu_fprintf(f, "PC=%08x\n", env->PC);
+ psw = psw_read(env);
+
+ cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
+ cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
+ cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
+ cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
+ cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
+ cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
+
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
- cpu_fprintf(f, "GPR A%02d:", i);
+ cpu_fprintf(f, "\nGPR A%02d:", i);
}
- cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
+ cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
}
for (i = 0; i < 16; ++i) {
if ((i & 3) == 0) {
- cpu_fprintf(f, "GPR D%02d:", i);
+ cpu_fprintf(f, "\nGPR D%02d:", i);
}
- cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
+ cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
}
-
+ cpu_fprintf(f, "\n");
}
/*
--
2.2.1
next prev parent reply other threads:[~2014-12-21 17:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-21 18:47 [Qemu-devel] [PULL 00/13] tricore patches Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 01/13] target-tricore: fix offset masking in BOL format Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 02/13] target-tricore: typo " Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format Bastian Koppelmann
2014-12-21 18:47 ` Bastian Koppelmann [this message]
2014-12-21 18:47 ` [Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being 7 bit long Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 06/13] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 07/13] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 08/13] target-tricore: Add instructions of RR opcode format, that have 0xf " Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 09/13] target-tricore: Add instructions of RR opcode format, that have 0x1 " Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 10/13] target-tricore: Add instructions of RR opcode format, that have 0x4b " Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 11/13] target-tricore: Add missing 1.6 insn of BOL opcode format Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 12/13] target-tricore: Fix MFCR/MTCR insn and B format offset Bastian Koppelmann
2014-12-21 18:47 ` [Qemu-devel] [PULL 13/13] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode Bastian Koppelmann
2014-12-22 14:52 ` [Qemu-devel] [PULL 00/13] tricore patches Peter Maydell
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