From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y766g-0006Rr-Ra for qemu-devel@nongnu.org; Fri, 02 Jan 2015 12:33:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y766d-000302-Ll for qemu-devel@nongnu.org; Fri, 02 Jan 2015 12:33:50 -0500 Received: from mx1.redhat.com ([209.132.183.28]:53209) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y766d-0002zo-EM for qemu-devel@nongnu.org; Fri, 02 Jan 2015 12:33:47 -0500 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t02HXkWr012544 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Fri, 2 Jan 2015 12:33:46 -0500 From: Andrew Jones Date: Fri, 2 Jan 2015 18:33:41 +0100 Message-Id: <1420220021-16886-1-git-send-email-drjones@redhat.com> Subject: [Qemu-devel] [PATCH] tcg-aarch64: handle additional PXN case List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org D4.5.1 "Memory access control:Access permissions for instruction execution" states "... In addition: * For the EL1&0 translation regime, if the value of the AP[2:1] bits is 0b01, permitting write access from EL0, then the PXN bit is treated as if it has the value 1, regardless of its actual value. ..." Signed-off-by: Andrew Jones --- target-arm/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3ef0f1f38eda5..962758888194a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4960,6 +4960,8 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) || (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) || + (arm_feature(env, ARM_FEATURE_V8) && !is_user && + ((attrs & (3 << 4)) == (1 << 4) /* AP[2:1] == 0b01 */)) || (!is_user && (attrs & (1 << 11)))) { /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally * treat XN/UXN as UXN for v8. -- 1.9.3