From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8sPn-0005sW-2o for qemu-devel@nongnu.org; Wed, 07 Jan 2015 10:21:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y8sPk-0003Dj-7d for qemu-devel@nongnu.org; Wed, 07 Jan 2015 10:20:55 -0500 From: Alexander Graf Date: Wed, 7 Jan 2015 16:20:34 +0100 Message-Id: <1420644048-16919-24-git-send-email-agraf@suse.de> In-Reply-To: <1420644048-16919-1-git-send-email-agraf@suse.de> References: <1420644048-16919-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 23/37] target-ppc: Power8 Supports Transactional Memory List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Tom Musta From: Tom Musta The Power8 processor implements the Transactional Memory Facility as defined in Power ISA 2.07. Update the initialization code to indicate this. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 1fece7b..72cc9d0 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8219,7 +8219,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | - PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64; + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM; pcc->msr_mask = (1ull << MSR_SF) | (1ull << MSR_TM) | (1ull << MSR_VR) | @@ -8247,7 +8248,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX; + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; pcc->l1_dcache_size = 0x8000; pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; -- 1.8.1.4