* [Qemu-devel] [PULL 01/37] PPC: e500: Move CCSR definition to params
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 02/37] PPC: e500: Move CCSR and MMIO space to upper end of address space Alexander Graf
` (36 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel
We want to have different MMIO region offsets for the mpc8544ds machine
and our e500 PV machine, so move the definitions of those into the machine
specific params struct.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/e500.c | 30 ++++++++++++++----------------
hw/ppc/e500.h | 3 +++
hw/ppc/e500plat.c | 3 +++
hw/ppc/mpc8544ds.c | 3 +++
4 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 2832fc0..1aaa515 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -51,19 +51,14 @@
#define RAM_SIZES_ALIGN (64UL << 20)
/* TODO: parameterize */
-#define MPC8544_CCSRBAR_BASE 0xE0000000ULL
#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
-#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
- MPC8544_PCI_REGS_OFFSET)
#define MPC8544_PCI_REGS_SIZE 0x1000ULL
-#define MPC8544_PCI_IO 0xE1000000ULL
#define MPC8544_UTIL_OFFSET 0xe0000ULL
-#define MPC8544_SPIN_BASE 0xEF000000ULL
#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
#define MPC8XXX_GPIO_IRQ 43
@@ -298,7 +293,7 @@ static int ppce500_load_device_tree(MachineState *machine,
0x0, 0x20000000,
0x1000000, 0x0, 0x0,
- 0x0, 0xe1000000,
+ params->pci_pio_base >> 32, params->pci_pio_base,
0x0, 0x10000,
};
QemuOpts *machine_opts = qemu_get_machine_opts();
@@ -389,7 +384,7 @@ static int ppce500_load_device_tree(MachineState *machine,
CPUState *cpu;
PowerPCCPU *pcpu;
char cpu_name[128];
- uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
+ uint64_t cpu_release_addr = params->spin_base + (i * 0x20);
cpu = qemu_get_cpu(i);
if (cpu == NULL) {
@@ -426,7 +421,7 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_add_subnode(fdt, "/aliases");
/* XXX These should go into their respective devices' code */
- snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
+ snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);
qemu_fdt_add_subnode(fdt, soc);
qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
@@ -434,7 +429,7 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
- MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
+ params->ccsrbar_base >> 32, params->ccsrbar_base,
MPC8544_CCSRBAR_SIZE);
/* XXX should contain a reasonable value */
qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
@@ -493,7 +488,8 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
- snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
+ snprintf(pci, sizeof(pci), "/pci@%llx",
+ params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
qemu_fdt_add_subnode(fdt, pci);
qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
@@ -512,8 +508,10 @@ static int ppce500_load_device_tree(MachineState *machine,
}
qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
- qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
- MPC8544_PCI_REGS_BASE, 0, 0x1000);
+ qemu_fdt_setprop_cells(fdt, pci, "reg",
+ (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
+ (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
+ 0, 0x1000);
qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
@@ -841,7 +839,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
- env->mpic_iack = MPC8544_CCSRBAR_BASE +
+ env->mpic_iack = params->ccsrbar_base +
MPC8544_MPIC_REGS_OFFSET + 0xa0;
ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
@@ -875,7 +873,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
qdev_init_nofail(dev);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
- memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
+ memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
ccsr_addr_space);
mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
@@ -917,7 +915,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
if (!pci_bus)
printf("couldn't create PCI controller!\n");
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base);
if (pci_bus) {
/* Register network interfaces. */
@@ -927,7 +925,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
}
/* Register spinning region */
- sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
+ sysbus_create_simple("e500-spin", params->spin_base, NULL);
if (cur_base < (32 * 1024 * 1024)) {
/* u-boot occupies memory up to 32MB, so load blobs above */
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 9f61ab2..d96f72d 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -17,6 +17,9 @@ typedef struct PPCE500Params {
hwaddr platform_bus_size;
int platform_bus_first_irq;
int platform_bus_num_irqs;
+ hwaddr ccsrbar_base;
+ hwaddr pci_pio_base;
+ hwaddr spin_base;
} PPCE500Params;
void ppce500_init(MachineState *machine, PPCE500Params *params);
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index d50ae00..1600fcf 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -41,6 +41,9 @@ static void e500plat_init(MachineState *machine)
.platform_bus_size = (128ULL * 1024 * 1024),
.platform_bus_first_irq = 5,
.platform_bus_num_irqs = 10,
+ .ccsrbar_base = 0xE0000000ULL,
+ .pci_pio_base = 0xE1000000ULL,
+ .spin_base = 0xEF000000ULL,
};
/* Older KVM versions don't support EPR which breaks guests when we announce
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index b99f74a..f131633 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -33,6 +33,9 @@ static void mpc8544ds_init(MachineState *machine)
.pci_nr_slots = 2,
.fixup_devtree = mpc8544ds_fixup_devtree,
.mpic_version = OPENPIC_MODEL_FSL_MPIC_20,
+ .ccsrbar_base = 0xE0000000ULL,
+ .pci_pio_base = 0xE1000000ULL,
+ .spin_base = 0xEF000000ULL,
};
ppce500_init(machine, ¶ms);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 02/37] PPC: e500: Move CCSR and MMIO space to upper end of address space
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 01/37] PPC: e500: Move CCSR definition to params Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 03/37] PPC: mpc8554ds: Tell user about exceeding RAM limits Alexander Graf
` (35 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel
On e500 we're basically guaranteed to have 36bits of physical address space
available for our enjoyment. Older chips (like the mpc8544) only had 32bits,
but everything from e500v2 onwards bumped it up.
It's reasonably safe to assume that if you're using the PV machine, your guest
kernel is configured to support 36bit physical address space. So in order to
support more guest RAM, we can move CCSR and other MMIO windows right below the
end of our 36bit address space, just like later SoC versions of e500 do.
With this patch, I'm able to successfully spawn an e500 VM with -m 48G.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/e500plat.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 1600fcf..1b8a68d 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -41,9 +41,9 @@ static void e500plat_init(MachineState *machine)
.platform_bus_size = (128ULL * 1024 * 1024),
.platform_bus_first_irq = 5,
.platform_bus_num_irqs = 10,
- .ccsrbar_base = 0xE0000000ULL,
- .pci_pio_base = 0xE1000000ULL,
- .spin_base = 0xEF000000ULL,
+ .ccsrbar_base = 0xFE0000000ULL,
+ .pci_pio_base = 0xFE1000000ULL,
+ .spin_base = 0xFEF000000ULL,
};
/* Older KVM versions don't support EPR which breaks guests when we announce
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 03/37] PPC: mpc8554ds: Tell user about exceeding RAM limits
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 01/37] PPC: e500: Move CCSR definition to params Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 02/37] PPC: e500: Move CCSR and MMIO space to upper end of address space Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 04/37] PPC: e500 pci host: Add support for ATMUs Alexander Graf
` (34 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel
The mpc8544ds board only supports up to 3GB of RAM due to its limited
address space.
When the user requests more, abort and tell him that he should use less.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/mpc8544ds.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index f131633..fb74b3f 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -15,6 +15,7 @@
#include "hw/boards.h"
#include "sysemu/device_tree.h"
#include "hw/ppc/openpic.h"
+#include "qemu/error-report.h"
static void mpc8544ds_fixup_devtree(PPCE500Params *params, void *fdt)
{
@@ -38,6 +39,11 @@ static void mpc8544ds_init(MachineState *machine)
.spin_base = 0xEF000000ULL,
};
+ if (machine->ram_size > 0xc0000000) {
+ error_report("The MPC8544DS board only supports up to 3GB of RAM");
+ exit(1);
+ }
+
ppce500_init(machine, ¶ms);
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 04/37] PPC: e500 pci host: Add support for ATMUs
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (2 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 03/37] PPC: mpc8554ds: Tell user about exceeding RAM limits Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 05/37] target-ppc: Load/Store Vector Element Storage Alignment Alexander Graf
` (33 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel
The e500 PCI controller has configurable windows that allow a guest OS
to selectively map parts of the PCI bus space to CPU address space and
to selectively map parts of the CPU address space for DMA requests into
PCI visible address ranges.
So far, we've simply assumed that this mapping is 1:1 and ignored it.
However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live
inside the first 32bits of address space. This means if we always treat
all mappings as 1:1, this map will collide with our RAM map from the CPU's
point of view.
So this patch adds proper ATMU support which allows us to keep the PCICSRBAR
below 32bits local to the PCI bus and have another, different window to PCI
BARs at the upper end of address space. We leverage this on e500plat though,
mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU.
With this patch, I can run guests with lots of RAM and not coincidently access
MSI-X mappings while I really want to access RAM.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/pci-host/ppce500.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++---
hw/ppc/e500.c | 6 +--
hw/ppc/e500.h | 2 +
hw/ppc/e500plat.c | 2 +
hw/ppc/mpc8544ds.c | 2 +
5 files changed, 115 insertions(+), 10 deletions(-)
diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index 1b4c0f0..574f8b2 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -62,11 +62,19 @@
#define PPCE500_PCI_NR_POBS 5
#define PPCE500_PCI_NR_PIBS 3
+#define PIWAR_EN 0x80000000 /* Enable */
+#define PIWAR_PF 0x20000000 /* prefetch */
+#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
+#define PIWAR_READ_SNOOP 0x00050000
+#define PIWAR_WRITE_SNOOP 0x00005000
+#define PIWAR_SZ_MASK 0x0000003f
+
struct pci_outbound {
uint32_t potar;
uint32_t potear;
uint32_t powbar;
uint32_t powar;
+ MemoryRegion mem;
};
struct pci_inbound {
@@ -74,6 +82,7 @@ struct pci_inbound {
uint32_t piwbar;
uint32_t piwbear;
uint32_t piwar;
+ MemoryRegion mem;
};
#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
@@ -91,10 +100,13 @@ struct PPCE500PCIState {
uint32_t irq_num[PCI_NUM_PINS];
uint32_t first_slot;
uint32_t first_pin_irq;
+ AddressSpace bm_as;
+ MemoryRegion bm;
/* mmio maps */
MemoryRegion container;
MemoryRegion iomem;
MemoryRegion pio;
+ MemoryRegion busmem;
};
#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
@@ -181,6 +193,71 @@ static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
return value;
}
+/* DMA mapping */
+static void e500_update_piw(PPCE500PCIState *pci, int idx)
+{
+ uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;
+ uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;
+ uint64_t war = pci->pib[idx].piwar;
+ uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *mem = &pci->pib[idx].mem;
+ MemoryRegion *bm = &pci->bm;
+ char *name;
+
+ if (memory_region_is_mapped(mem)) {
+ /* Before we modify anything, unmap and destroy the region */
+ memory_region_del_subregion(bm, mem);
+ object_unparent(OBJECT(mem));
+ }
+
+ if (!(war & PIWAR_EN)) {
+ /* Not enabled, nothing to do */
+ return;
+ }
+
+ name = g_strdup_printf("PCI Inbound Window %d", idx);
+ memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,
+ size);
+ memory_region_add_subregion_overlap(bm, wbar, mem, -1);
+ g_free(name);
+
+ pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",
+ __func__, size, wbar, tar);
+}
+
+/* BAR mapping */
+static void e500_update_pow(PPCE500PCIState *pci, int idx)
+{
+ uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;
+ uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;
+ uint64_t war = pci->pob[idx].powar;
+ uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
+ MemoryRegion *mem = &pci->pob[idx].mem;
+ MemoryRegion *address_space_mem = get_system_memory();
+ char *name;
+
+ if (memory_region_is_mapped(mem)) {
+ /* Before we modify anything, unmap and destroy the region */
+ memory_region_del_subregion(address_space_mem, mem);
+ object_unparent(OBJECT(mem));
+ }
+
+ if (!(war & PIWAR_EN)) {
+ /* Not enabled, nothing to do */
+ return;
+ }
+
+ name = g_strdup_printf("PCI Outbound Window %d", idx);
+ memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,
+ size);
+ memory_region_add_subregion(address_space_mem, wbar, mem);
+ g_free(name);
+
+ pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",
+ __func__, size, wbar, tar);
+}
+
static void pci_reg_write4(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
@@ -199,18 +276,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr,
case PPCE500_PCI_OW3:
case PPCE500_PCI_OW4:
idx = (addr >> 5) & 0x7;
- switch (addr & 0xC) {
+ switch (addr & 0x1F) {
case PCI_POTAR:
pci->pob[idx].potar = value;
+ e500_update_pow(pci, idx);
break;
case PCI_POTEAR:
pci->pob[idx].potear = value;
+ e500_update_pow(pci, idx);
break;
case PCI_POWBAR:
pci->pob[idx].powbar = value;
+ e500_update_pow(pci, idx);
break;
case PCI_POWAR:
pci->pob[idx].powar = value;
+ e500_update_pow(pci, idx);
break;
default:
break;
@@ -221,18 +302,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr,
case PPCE500_PCI_IW2:
case PPCE500_PCI_IW1:
idx = ((addr >> 5) & 0x3) - 1;
- switch (addr & 0xC) {
+ switch (addr & 0x1F) {
case PCI_PITAR:
pci->pib[idx].pitar = value;
+ e500_update_piw(pci, idx);
break;
case PCI_PIWBAR:
pci->pib[idx].piwbar = value;
+ e500_update_piw(pci, idx);
break;
case PCI_PIWBEAR:
pci->pib[idx].piwbear = value;
+ e500_update_piw(pci, idx);
break;
case PCI_PIWAR:
pci->pib[idx].piwar = value;
+ e500_update_piw(pci, idx);
break;
default:
break;
@@ -349,13 +434,20 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d)
return 0;
}
+static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
+ int devfn)
+{
+ PPCE500PCIState *s = opaque;
+
+ return &s->bm_as;
+}
+
static int e500_pcihost_initfn(SysBusDevice *dev)
{
PCIHostState *h;
PPCE500PCIState *s;
PCIBus *b;
int i;
- MemoryRegion *address_space_mem = get_system_memory();
h = PCI_HOST_BRIDGE(dev);
s = PPC_E500_PCI_HOST_BRIDGE(dev);
@@ -369,12 +461,22 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
}
memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
+ memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);
+
+ /* PIO lives at the bottom of our bus space */
+ memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
- mpc85xx_pci_map_irq, s, address_space_mem,
- &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
+ mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
+ PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
h->bus = b;
+ /* Set up PCI view of memory */
+ memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);
+ memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
+ address_space_init(&s->bm_as, &s->bm, "pci-bm");
+ pci_setup_iommu(b, e500_pcihost_set_iommu, s);
+
pci_create_simple(b, 0, "e500-host-bridge");
memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
@@ -388,7 +490,6 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
sysbus_init_mmio(dev, &s->container);
- sysbus_init_mmio(dev, &s->pio);
pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
return 0;
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 1aaa515..a2e60b4 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -288,8 +288,8 @@ static int ppce500_load_device_tree(MachineState *machine,
int len;
uint32_t pci_ranges[14] =
{
- 0x2000000, 0x0, 0xc0000000,
- 0x0, 0xc0000000,
+ 0x2000000, 0x0, params->pci_mmio_bus_base,
+ params->pci_mmio_base >> 32, params->pci_mmio_base,
0x0, 0x20000000,
0x1000000, 0x0, 0x0,
@@ -915,8 +915,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
if (!pci_bus)
printf("couldn't create PCI controller!\n");
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base);
-
if (pci_bus) {
/* Register network interfaces. */
for (i = 0; i < nb_nics; i++) {
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index d96f72d..ef224ea 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -19,6 +19,8 @@ typedef struct PPCE500Params {
int platform_bus_num_irqs;
hwaddr ccsrbar_base;
hwaddr pci_pio_base;
+ hwaddr pci_mmio_base;
+ hwaddr pci_mmio_bus_base;
hwaddr spin_base;
} PPCE500Params;
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 1b8a68d..14b14ea 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -43,6 +43,8 @@ static void e500plat_init(MachineState *machine)
.platform_bus_num_irqs = 10,
.ccsrbar_base = 0xFE0000000ULL,
.pci_pio_base = 0xFE1000000ULL,
+ .pci_mmio_base = 0xC00000000ULL,
+ .pci_mmio_bus_base = 0xE0000000ULL,
.spin_base = 0xFEF000000ULL,
};
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index fb74b3f..3a3b141 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -35,6 +35,8 @@ static void mpc8544ds_init(MachineState *machine)
.fixup_devtree = mpc8544ds_fixup_devtree,
.mpic_version = OPENPIC_MODEL_FSL_MPIC_20,
.ccsrbar_base = 0xE0000000ULL,
+ .pci_mmio_base = 0xC0000000ULL,
+ .pci_mmio_bus_base = 0xC0000000ULL,
.pci_pio_base = 0xE1000000ULL,
.spin_base = 0xEF000000ULL,
};
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 05/37] target-ppc: Load/Store Vector Element Storage Alignment
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (3 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 04/37] PPC: e500 pci host: Add support for ATMUs Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs Alexander Graf
` (32 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
The Load Vector Element Indexed and Store Vector Element Indexed
instructions compute an effective address in the usual manner.
However, they truncate that address to the natural boundary.
For example, the lvewx instruction will ignore the least significant
two bits of the address and thus load the aligned word of storage.
Fix the generators for these instruction to properly perform this
truncation.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d381632..fe36b58 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6743,7 +6743,7 @@ static void gen_st##name(DisasContext *ctx) \
tcg_temp_free(EA); \
}
-#define GEN_VR_LVE(name, opc2, opc3) \
+#define GEN_VR_LVE(name, opc2, opc3, size) \
static void gen_lve##name(DisasContext *ctx) \
{ \
TCGv EA; \
@@ -6755,13 +6755,16 @@ static void gen_lve##name(DisasContext *ctx) \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
+ if (size > 1) { \
+ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
+ } \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_lve##name(cpu_env, rs, EA); \
tcg_temp_free(EA); \
tcg_temp_free_ptr(rs); \
}
-#define GEN_VR_STVE(name, opc2, opc3) \
+#define GEN_VR_STVE(name, opc2, opc3, size) \
static void gen_stve##name(DisasContext *ctx) \
{ \
TCGv EA; \
@@ -6773,6 +6776,9 @@ static void gen_stve##name(DisasContext *ctx) \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
+ if (size > 1) { \
+ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
+ } \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_stve##name(cpu_env, rs, EA); \
tcg_temp_free(EA); \
@@ -6783,17 +6789,17 @@ GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B);
-GEN_VR_LVE(bx, 0x07, 0x00);
-GEN_VR_LVE(hx, 0x07, 0x01);
-GEN_VR_LVE(wx, 0x07, 0x02);
+GEN_VR_LVE(bx, 0x07, 0x00, 1);
+GEN_VR_LVE(hx, 0x07, 0x01, 2);
+GEN_VR_LVE(wx, 0x07, 0x02, 4);
GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
-GEN_VR_STVE(bx, 0x07, 0x04);
-GEN_VR_STVE(hx, 0x07, 0x05);
-GEN_VR_STVE(wx, 0x07, 0x06);
+GEN_VR_STVE(bx, 0x07, 0x04, 1);
+GEN_VR_STVE(hx, 0x07, 0x05, 2);
+GEN_VR_STVE(wx, 0x07, 0x06, 4);
static void gen_lvsl(DisasContext *ctx)
{
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (4 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 05/37] target-ppc: Load/Store Vector Element Storage Alignment Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-02-12 22:21 ` Maciej W. Rozycki
2015-01-07 15:20 ` [Qemu-devel] [PULL 07/37] target-ppc: Fix Floating Point Move Instructions That Set CR1 Alexander Graf
` (31 subsequent siblings)
37 siblings, 1 reply; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
The Power ISA square root instructions (fsqrt[s], frsqrte[s]) must
set the FPSCR[VXSQRT] flag when operating on a negative value.
However, NaNs have no sign and therefore this flag should not
be set when operating on one.
Change the order of the checks in the helper code. Move the
SNaN-to-QNaN macro to the top of the file so that it can be
re-used.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/fpu_helper.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 7f74466..81db60f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -19,6 +19,9 @@
#include "cpu.h"
#include "exec/helper-proto.h"
+#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
+#define float32_snan_to_qnan(x) ((x) | 0x00400000)
+
/*****************************************************************************/
/* Floating point operations helpers */
uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
@@ -920,14 +923,16 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
- if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
- /* Square root of a negative nonzero number */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
- } else {
+ if (unlikely(float64_is_any_nan(farg.d))) {
if (unlikely(float64_is_signaling_nan(farg.d))) {
- /* sNaN square root */
+ /* sNaN reciprocal square root */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ farg.ll = float64_snan_to_qnan(farg.ll);
}
+ } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
+ /* Square root of a negative nonzero number */
+ farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
+ } else {
farg.d = float64_sqrt(farg.d, &env->fp_status);
}
return farg.ll;
@@ -974,17 +979,20 @@ uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
farg.ll = arg;
- if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
- /* Reciprocal square root of a negative nonzero number */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
- } else {
+ if (unlikely(float64_is_any_nan(farg.d))) {
if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN reciprocal square root */
fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ farg.ll = float64_snan_to_qnan(farg.ll);
}
+ } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
+ /* Reciprocal square root of a negative nonzero number */
+ farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
+ } else {
farg.d = float64_sqrt(farg.d, &env->fp_status);
farg.d = float64_div(float64_one, farg.d, &env->fp_status);
}
+
return farg.ll;
}
@@ -2382,9 +2390,6 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
VSX_SCALAR_CMP(xscmpodp, 1)
VSX_SCALAR_CMP(xscmpudp, 0)
-#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
-#define float32_snan_to_qnan(x) ((x) | 0x00400000)
-
/* VSX_MAX_MIN - VSX floating point maximum/minimum
* name - instruction mnemonic
* op - operation (max or min)
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs
2015-01-07 15:20 ` [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs Alexander Graf
@ 2015-02-12 22:21 ` Maciej W. Rozycki
2015-02-13 14:28 ` Tom Musta
2015-02-13 23:35 ` Alexander Graf
0 siblings, 2 replies; 42+ messages in thread
From: Maciej W. Rozycki @ 2015-02-12 22:21 UTC (permalink / raw)
To: Alexander Graf; +Cc: peter.maydell, qemu-ppc, qemu-devel, Tom Musta
On Wed, 7 Jan 2015, Alexander Graf wrote:
> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> index 7f74466..81db60f 100644
> --- a/target-ppc/fpu_helper.c
> +++ b/target-ppc/fpu_helper.c
> @@ -920,14 +923,16 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
>
> farg.ll = arg;
>
> - if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
> - /* Square root of a negative nonzero number */
> - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> - } else {
> + if (unlikely(float64_is_any_nan(farg.d))) {
> if (unlikely(float64_is_signaling_nan(farg.d))) {
> - /* sNaN square root */
> + /* sNaN reciprocal square root */
This change to the comment looks accidental, compare the changes below.
Should it be reverted? [Found this while resolving merge conflicts.]
> fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
> + farg.ll = float64_snan_to_qnan(farg.ll);
> }
> + } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
> + /* Square root of a negative nonzero number */
> + farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> + } else {
> farg.d = float64_sqrt(farg.d, &env->fp_status);
> }
> return farg.ll;
> @@ -974,17 +979,20 @@ uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
>
> farg.ll = arg;
>
> - if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
> - /* Reciprocal square root of a negative nonzero number */
> - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> - } else {
> + if (unlikely(float64_is_any_nan(farg.d))) {
> if (unlikely(float64_is_signaling_nan(farg.d))) {
> /* sNaN reciprocal square root */
> fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
> + farg.ll = float64_snan_to_qnan(farg.ll);
> }
> + } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
> + /* Reciprocal square root of a negative nonzero number */
> + farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> + } else {
> farg.d = float64_sqrt(farg.d, &env->fp_status);
> farg.d = float64_div(float64_one, farg.d, &env->fp_status);
> }
> +
> return farg.ll;
> }
>
Maciej
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs
2015-02-12 22:21 ` Maciej W. Rozycki
@ 2015-02-13 14:28 ` Tom Musta
2015-02-13 23:35 ` Alexander Graf
1 sibling, 0 replies; 42+ messages in thread
From: Tom Musta @ 2015-02-13 14:28 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: Peter Maydell, qemu-ppc@nongnu.org, Alexander Graf,
QEMU Developers
[-- Attachment #1: Type: text/plain, Size: 2687 bytes --]
I agree that the comment is incorrect and should say "sNaN square root".
On Thu, Feb 12, 2015 at 4:21 PM, Maciej W. Rozycki <macro@linux-mips.org>
wrote:
> On Wed, 7 Jan 2015, Alexander Graf wrote:
>
> > diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> > index 7f74466..81db60f 100644
> > --- a/target-ppc/fpu_helper.c
> > +++ b/target-ppc/fpu_helper.c
> > @@ -920,14 +923,16 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t
> arg)
> >
> > farg.ll = arg;
> >
> > - if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
> > - /* Square root of a negative nonzero number */
> > - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> > - } else {
> > + if (unlikely(float64_is_any_nan(farg.d))) {
> > if (unlikely(float64_is_signaling_nan(farg.d))) {
> > - /* sNaN square root */
> > + /* sNaN reciprocal square root */
>
> This change to the comment looks accidental, compare the changes below.
> Should it be reverted? [Found this while resolving merge conflicts.]
>
> > fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
> > + farg.ll = float64_snan_to_qnan(farg.ll);
> > }
> > + } else if (unlikely(float64_is_neg(farg.d) &&
> !float64_is_zero(farg.d))) {
> > + /* Square root of a negative nonzero number */
> > + farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> > + } else {
> > farg.d = float64_sqrt(farg.d, &env->fp_status);
> > }
> > return farg.ll;
> > @@ -974,17 +979,20 @@ uint64_t helper_frsqrte(CPUPPCState *env, uint64_t
> arg)
> >
> > farg.ll = arg;
> >
> > - if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
> > - /* Reciprocal square root of a negative nonzero number */
> > - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> > - } else {
> > + if (unlikely(float64_is_any_nan(farg.d))) {
> > if (unlikely(float64_is_signaling_nan(farg.d))) {
> > /* sNaN reciprocal square root */
> > fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
> > + farg.ll = float64_snan_to_qnan(farg.ll);
> > }
> > + } else if (unlikely(float64_is_neg(farg.d) &&
> !float64_is_zero(farg.d))) {
> > + /* Reciprocal square root of a negative nonzero number */
> > + farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
> > + } else {
> > farg.d = float64_sqrt(farg.d, &env->fp_status);
> > farg.d = float64_div(float64_one, farg.d, &env->fp_status);
> > }
> > +
> > return farg.ll;
> > }
> >
>
> Maciej
>
[-- Attachment #2: Type: text/html, Size: 3672 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs
2015-02-12 22:21 ` Maciej W. Rozycki
2015-02-13 14:28 ` Tom Musta
@ 2015-02-13 23:35 ` Alexander Graf
1 sibling, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-02-13 23:35 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: peter.maydell, qemu-ppc, qemu-devel, Tom Musta
On 12.02.15 23:21, Maciej W. Rozycki wrote:
> On Wed, 7 Jan 2015, Alexander Graf wrote:
>
>> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
>> index 7f74466..81db60f 100644
>> --- a/target-ppc/fpu_helper.c
>> +++ b/target-ppc/fpu_helper.c
>> @@ -920,14 +923,16 @@ uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
>>
>> farg.ll = arg;
>>
>> - if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
>> - /* Square root of a negative nonzero number */
>> - farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
>> - } else {
>> + if (unlikely(float64_is_any_nan(farg.d))) {
>> if (unlikely(float64_is_signaling_nan(farg.d))) {
>> - /* sNaN square root */
>> + /* sNaN reciprocal square root */
>
> This change to the comment looks accidental, compare the changes below.
> Should it be reverted? [Found this while resolving merge conflicts.]
Nicely spotted. Could you please cook up a small patch fixing it?
Thanks!
Alex
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PULL 07/37] target-ppc: Fix Floating Point Move Instructions That Set CR1
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (5 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 08/37] target-ppc: mffs. Should Set CR1 from FPSCR Bits Alexander Graf
` (30 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
The Floating Point Move instructions (fmr., fabs., fnabs., fneg.,
and fcpsgn.) incorrectly copy FPSCR[FPCC] instead of [FX,FEX,VX,OX].
Furthermore, the current code does this via a call to gen_compute_fprf,
which is awkward since these instructions do not actually set FPRF.
Change the code to use the gen_set_cr1_from_fpscr utility.
Signed-off-by: Tom Musta <tommusta@gmail.com>
[agraf: whitespace fixes]
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 50 ++++++++++++++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 20 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fe36b58..35c3a16 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2077,6 +2077,21 @@ static void gen_srd(DisasContext *ctx)
}
#endif
+#if defined(TARGET_PPC64)
+static void gen_set_cr1_from_fpscr(DisasContext *ctx)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
+ tcg_temp_free_i32(tmp);
+}
+#else
+static void gen_set_cr1_from_fpscr(DisasContext *ctx)
+{
+ tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
+}
+#endif
+
/*** Floating-Point arithmetic ***/
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
static void gen_f##name(DisasContext *ctx) \
@@ -2370,7 +2385,9 @@ static void gen_fabs(DisasContext *ctx)
}
tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
~(1ULL << 63));
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
/* fmr - fmr. */
@@ -2382,7 +2399,9 @@ static void gen_fmr(DisasContext *ctx)
return;
}
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
/* fnabs */
@@ -2395,7 +2414,9 @@ static void gen_fnabs(DisasContext *ctx)
}
tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
1ULL << 63);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
/* fneg */
@@ -2408,7 +2429,9 @@ static void gen_fneg(DisasContext *ctx)
}
tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
1ULL << 63);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
/* fcpsgn: PowerPC 2.05 specification */
@@ -2421,7 +2444,9 @@ static void gen_fcpsgn(DisasContext *ctx)
}
tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
cpu_fpr[rB(ctx->opcode)], 0, 63);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
static void gen_fmrgew(DisasContext *ctx)
@@ -8211,21 +8236,6 @@ static inline TCGv_ptr gen_fprp_ptr(int reg)
return r;
}
-#if defined(TARGET_PPC64)
-static void gen_set_cr1_from_fpscr(DisasContext *ctx)
-{
- TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
- tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
- tcg_temp_free_i32(tmp);
-}
-#else
-static void gen_set_cr1_from_fpscr(DisasContext *ctx)
-{
- tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
-}
-#endif
-
#define GEN_DFP_T_A_B_Rc(name) \
static void gen_##name(DisasContext *ctx) \
{ \
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 08/37] target-ppc: mffs. Should Set CR1 from FPSCR Bits
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (6 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 07/37] target-ppc: Fix Floating Point Move Instructions That Set CR1 Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 09/37] target-ppc: Fully Migrate to gen_set_cr1_from_fpscr Alexander Graf
` (29 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Update the Move From FPSCR (mffs.) instruction to correctly
set CR[1] from FPSCR[FX,FEX,VX,OX].
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 35c3a16..32c9f49 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2504,7 +2504,9 @@ static void gen_mffs(DisasContext *ctx)
}
gen_reset_fpstatus();
tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+ if (unlikely(Rc(ctx->opcode))) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
/* mtfsb0 */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 09/37] target-ppc: Fully Migrate to gen_set_cr1_from_fpscr
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (7 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 08/37] target-ppc: mffs. Should Set CR1 from FPSCR Bits Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 10/37] target-ppc: Eliminate set_fprf Argument From gen_compute_fprf Alexander Graf
` (28 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Eliminate the set_rc argument from the gen_compute_fprf utility and
the corresponding (and incorrect) implementation. Replace it with
calls to the gen_set_cr1_from_fpscr() utility.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 55 ++++++++++++++++++++++++++++++--------------------
1 file changed, 33 insertions(+), 22 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 32c9f49..18cd8c4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -250,7 +250,7 @@ static inline void gen_reset_fpstatus(void)
gen_helper_reset_fpstatus(cpu_env);
}
-static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
+static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf)
{
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -258,15 +258,7 @@ static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
/* This case might be optimized later */
tcg_gen_movi_i32(t0, 1);
gen_helper_compute_fprf(t0, cpu_env, arg, t0);
- if (unlikely(set_rc)) {
- tcg_gen_mov_i32(cpu_crf[1], t0);
- }
gen_helper_float_check_status(cpu_env);
- } else if (unlikely(set_rc)) {
- /* We always need to compute fpcc */
- tcg_gen_movi_i32(t0, 0);
- gen_helper_compute_fprf(t0, cpu_env, arg, t0);
- tcg_gen_mov_i32(cpu_crf[1], t0);
}
tcg_temp_free_i32(t0);
@@ -2110,8 +2102,10 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rD(ctx->opcode)]); \
} \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
- Rc(ctx->opcode) != 0); \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
}
#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
@@ -2135,8 +2129,10 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rD(ctx->opcode)]); \
} \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
- set_fprf, Rc(ctx->opcode) != 0); \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
}
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
@@ -2159,8 +2155,10 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rD(ctx->opcode)]); \
} \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
- set_fprf, Rc(ctx->opcode) != 0); \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
}
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
@@ -2178,8 +2176,10 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
- set_fprf, Rc(ctx->opcode) != 0); \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
}
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
@@ -2194,8 +2194,10 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
- set_fprf, Rc(ctx->opcode) != 0); \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (unlikely(Rc(ctx->opcode) != 0)) { \
+ gen_set_cr1_from_fpscr(ctx); \
+ } \
}
/* fadd - fadds */
@@ -2228,7 +2230,10 @@ static void gen_frsqrtes(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
/* fsel */
@@ -2249,7 +2254,10 @@ static void gen_fsqrt(DisasContext *ctx)
gen_reset_fpstatus();
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rB(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
static void gen_fsqrts(DisasContext *ctx)
@@ -2265,7 +2273,10 @@ static void gen_fsqrts(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
}
/*** Floating-Point multiply-and-add ***/
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 10/37] target-ppc: Eliminate set_fprf Argument From gen_compute_fprf
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (8 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 09/37] target-ppc: Fully Migrate to gen_set_cr1_from_fpscr Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 11/37] target-ppc: Eliminate set_fprf Argument From helper_compute_fprf Alexander Graf
` (27 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
The set_fprf argument to the gen_compute_fprf() utility is no longer
needed -- gen_compute_fprf() is now called only when FPRF is actually
computed and set. Eliminate the obsolete argument.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 38 +++++++++++++++++++++++---------------
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 18cd8c4..598f02e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -250,16 +250,14 @@ static inline void gen_reset_fpstatus(void)
gen_helper_reset_fpstatus(cpu_env);
}
-static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf)
+static inline void gen_compute_fprf(TCGv_i64 arg)
{
TCGv_i32 t0 = tcg_temp_new_i32();
- if (set_fprf != 0) {
- /* This case might be optimized later */
- tcg_gen_movi_i32(t0, 1);
- gen_helper_compute_fprf(t0, cpu_env, arg, t0);
- gen_helper_float_check_status(cpu_env);
- }
+ /* This case might be optimized later */
+ tcg_gen_movi_i32(t0, 1);
+ gen_helper_compute_fprf(t0, cpu_env, arg, t0);
+ gen_helper_float_check_status(cpu_env);
tcg_temp_free_i32(t0);
}
@@ -2102,7 +2100,9 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rD(ctx->opcode)]); \
} \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (set_fprf) { \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ } \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -2129,7 +2129,9 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rD(ctx->opcode)]); \
} \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (set_fprf) { \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ } \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -2155,7 +2157,9 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rD(ctx->opcode)]); \
} \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (set_fprf) { \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ } \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -2176,7 +2180,9 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (set_fprf) { \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ } \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -2194,7 +2200,9 @@ static void gen_f##name(DisasContext *ctx) \
gen_reset_fpstatus(); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf); \
+ if (set_fprf) { \
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ } \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
@@ -2230,7 +2238,7 @@ static void gen_frsqrtes(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
@@ -2254,7 +2262,7 @@ static void gen_fsqrt(DisasContext *ctx)
gen_reset_fpstatus();
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rB(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
@@ -2273,7 +2281,7 @@ static void gen_fsqrts(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 11/37] target-ppc: Eliminate set_fprf Argument From helper_compute_fprf
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (9 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 10/37] target-ppc: Eliminate set_fprf Argument From gen_compute_fprf Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 12/37] target-ppc: explicitly save page table headers in big endian Alexander Graf
` (26 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
The set_fprf argument to the helper_compute_fprf helper function
is no longer necessary -- the helper is only invoked when FPSCR[FPRF]
is going to be set.
Eliminate the unnecessary argument from the function signature and
its corresponding implementation. Change the return value of the
helper to "void". Update the name of the local variable "ret" to
"fprf", which now makes more sense.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/fpu_helper.c | 56 +++++++++++++++++++++++--------------------------
target-ppc/helper.h | 2 +-
target-ppc/translate.c | 8 +------
3 files changed, 28 insertions(+), 38 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 81db60f..6cceffc 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -63,59 +63,55 @@ static inline int ppc_float64_get_unbiased_exp(float64 f)
return ((f >> 52) & 0x7FF) - 1023;
}
-uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
+void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
{
CPU_DoubleU farg;
int isneg;
- int ret;
+ int fprf;
farg.ll = arg;
isneg = float64_is_neg(farg.d);
if (unlikely(float64_is_any_nan(farg.d))) {
if (float64_is_signaling_nan(farg.d)) {
/* Signaling NaN: flags are undefined */
- ret = 0x00;
+ fprf = 0x00;
} else {
/* Quiet NaN */
- ret = 0x11;
+ fprf = 0x11;
}
} else if (unlikely(float64_is_infinity(farg.d))) {
/* +/- infinity */
if (isneg) {
- ret = 0x09;
+ fprf = 0x09;
} else {
- ret = 0x05;
+ fprf = 0x05;
}
} else {
if (float64_is_zero(farg.d)) {
/* +/- zero */
if (isneg) {
- ret = 0x12;
+ fprf = 0x12;
} else {
- ret = 0x02;
+ fprf = 0x02;
}
} else {
if (isden(farg.d)) {
/* Denormalized numbers */
- ret = 0x10;
+ fprf = 0x10;
} else {
/* Normalized numbers */
- ret = 0x00;
+ fprf = 0x00;
}
if (isneg) {
- ret |= 0x08;
+ fprf |= 0x08;
} else {
- ret |= 0x04;
+ fprf |= 0x04;
}
}
}
- if (set_fprf) {
- /* We update FPSCR_FPRF */
- env->fpscr &= ~(0x1F << FPSCR_FPRF);
- env->fpscr |= ret << FPSCR_FPRF;
- }
- /* We just need fpcc to update Rc1 */
- return ret & 0xF;
+ /* We update FPSCR_FPRF */
+ env->fpscr &= ~(0x1F << FPSCR_FPRF);
+ env->fpscr |= fprf << FPSCR_FPRF;
}
/* Floating-point invalid operations exception */
@@ -1853,7 +1849,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld, sfprf); \
+ helper_compute_fprf(env, xt.fld); \
} \
} \
putVSR(xT(opcode), &xt, env); \
@@ -1908,7 +1904,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld, sfprf); \
+ helper_compute_fprf(env, xt.fld); \
} \
} \
\
@@ -1962,7 +1958,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld, sfprf); \
+ helper_compute_fprf(env, xt.fld); \
} \
} \
\
@@ -2003,7 +1999,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld, sfprf); \
+ helper_compute_fprf(env, xt.fld); \
} \
} \
\
@@ -2052,7 +2048,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld, sfprf); \
+ helper_compute_fprf(env, xt.fld); \
} \
} \
\
@@ -2102,7 +2098,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld, sfprf); \
+ helper_compute_fprf(env, xt.fld); \
} \
} \
\
@@ -2302,7 +2298,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt_out.fld, sfprf); \
+ helper_compute_fprf(env, xt_out.fld); \
} \
} \
putVSR(xT(opcode), &xt_out, env); \
@@ -2509,7 +2505,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
if (sfprf) { \
helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
- &env->fp_status), sfprf); \
+ &env->fp_status)); \
} \
} \
\
@@ -2619,7 +2615,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.tfld = helper_frsp(env, xt.tfld); \
} \
if (sfprf) { \
- helper_compute_fprf(env, xt.tfld, sfprf); \
+ helper_compute_fprf(env, xt.tfld); \
} \
} \
\
@@ -2674,7 +2670,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \
} \
if (sfprf) { \
- helper_compute_fprf(env, xt.fld, sfprf); \
+ helper_compute_fprf(env, xt.fld); \
} \
} \
\
@@ -2714,7 +2710,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
uint64_t xt = helper_frsp(env, xb);
- helper_compute_fprf(env, xt, 1);
+ helper_compute_fprf(env, xt);
helper_float_check_status(env);
return xt;
}
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 210fd97..2841f61 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -52,7 +52,7 @@ DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_1(float_check_status, void, env)
DEF_HELPER_1(reset_fpstatus, void, env)
-DEF_HELPER_3(compute_fprf, i32, env, i64, i32)
+DEF_HELPER_2(compute_fprf, void, env, i64)
DEF_HELPER_3(store_fpscr, void, env, i64, i32)
DEF_HELPER_2(fpscr_clrbit, void, env, i32)
DEF_HELPER_2(fpscr_setbit, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 598f02e..a772382 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -252,14 +252,8 @@ static inline void gen_reset_fpstatus(void)
static inline void gen_compute_fprf(TCGv_i64 arg)
{
- TCGv_i32 t0 = tcg_temp_new_i32();
-
- /* This case might be optimized later */
- tcg_gen_movi_i32(t0, 1);
- gen_helper_compute_fprf(t0, cpu_env, arg, t0);
+ gen_helper_compute_fprf(cpu_env, arg);
gen_helper_float_check_status(cpu_env);
-
- tcg_temp_free_i32(t0);
}
static inline void gen_set_access_type(DisasContext *ctx, int access_type)
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 12/37] target-ppc: explicitly save page table headers in big endian
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (10 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 11/37] target-ppc: Eliminate set_fprf Argument From helper_compute_fprf Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 13/37] spapr: Fix stale HTAB during live migration (KVM) Alexander Graf
` (25 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, Cédric Le Goater, qemu-devel
From: Cédric Le Goater <clg@fr.ibm.com>
Currently, when the page tables are saved, the kvm_get_htab_header structs
and the ptes are assumed being big endian and dumped as a indistinct blob
in the statefile. This is no longer true when the host is little endian
and this breaks restoration.
This patch unfolds the kvmppc_save_htab routine to write explicitly the
kvm_get_htab_header structs in big endian. The ptes are left untouched.
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/kvm.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 6843fa0..911f912 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -2246,8 +2246,23 @@ int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
strerror(errno));
return rc;
} else if (rc) {
- /* Kernel already retuns data in BE format for the file */
- qemu_put_buffer(f, buf, rc);
+ uint8_t *buffer = buf;
+ ssize_t n = rc;
+ while (n) {
+ struct kvm_get_htab_header *head =
+ (struct kvm_get_htab_header *) buffer;
+ size_t chunksize = sizeof(*head) +
+ HASH_PTE_SIZE_64 * head->n_valid;
+
+ qemu_put_be32(f, head->index);
+ qemu_put_be16(f, head->n_valid);
+ qemu_put_be16(f, head->n_invalid);
+ qemu_put_buffer(f, (void *)(head + 1),
+ HASH_PTE_SIZE_64 * head->n_valid);
+
+ buffer += chunksize;
+ n -= chunksize;
+ }
}
} while ((rc != 0)
&& ((max_ns < 0)
@@ -2264,7 +2279,6 @@ int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
ssize_t rc;
buf = alloca(chunksize);
- /* This is KVM on ppc, so this is all big-endian */
buf->index = index;
buf->n_valid = n_valid;
buf->n_invalid = n_invalid;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 13/37] spapr: Fix stale HTAB during live migration (KVM)
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (11 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 12/37] target-ppc: explicitly save page table headers in big endian Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 14/37] spapr: Fix integer overflow during migration (TCG) Alexander Graf
` (24 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, Samuel Mendoza-Jonas, qemu-devel
From: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
If a guest reboots during a running migration, changes to the
hash page table are not necessarily updated on the destination.
Opening a new file descriptor to the HTAB forces the migration
handler to resend the entire table.
Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr.c | 38 ++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 08401e0..869b721 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -833,6 +833,11 @@ static void spapr_reset_htab(sPAPREnvironment *spapr)
/* Kernel handles htab, we don't need to allocate one */
spapr->htab_shift = shift;
kvmppc_kern_htab = true;
+
+ /* Tell readers to update their file descriptor */
+ if (spapr->htab_fd >= 0) {
+ spapr->htab_fd_stale = true;
+ }
} else {
if (!spapr->htab) {
/* Allocate an htab if we don't yet have one */
@@ -867,6 +872,28 @@ static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
return 0;
}
+/*
+ * A guest reset will cause spapr->htab_fd to become stale if being used.
+ * Reopen the file descriptor to make sure the whole HTAB is properly read.
+ */
+static int spapr_check_htab_fd(sPAPREnvironment *spapr)
+{
+ int rc = 0;
+
+ if (spapr->htab_fd_stale) {
+ close(spapr->htab_fd);
+ spapr->htab_fd = kvmppc_get_htab_fd(false);
+ if (spapr->htab_fd < 0) {
+ error_report("Unable to open fd for reading hash table from KVM: "
+ "%s", strerror(errno));
+ rc = -1;
+ }
+ spapr->htab_fd_stale = false;
+ }
+
+ return rc;
+}
+
static void ppc_spapr_reset(void)
{
PowerPCCPU *first_ppc_cpu;
@@ -1005,6 +1032,7 @@ static int htab_save_setup(QEMUFile *f, void *opaque)
assert(kvm_enabled());
spapr->htab_fd = kvmppc_get_htab_fd(false);
+ spapr->htab_fd_stale = false;
if (spapr->htab_fd < 0) {
fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n",
strerror(errno));
@@ -1157,6 +1185,11 @@ static int htab_save_iterate(QEMUFile *f, void *opaque)
if (!spapr->htab) {
assert(kvm_enabled());
+ rc = spapr_check_htab_fd(spapr);
+ if (rc < 0) {
+ return rc;
+ }
+
rc = kvmppc_save_htab(f, spapr->htab_fd,
MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
if (rc < 0) {
@@ -1188,6 +1221,11 @@ static int htab_save_complete(QEMUFile *f, void *opaque)
assert(kvm_enabled());
+ rc = spapr_check_htab_fd(spapr);
+ if (rc < 0) {
+ return rc;
+ }
+
rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1);
if (rc < 0) {
return rc;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 749daf4..716bff4 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -37,6 +37,7 @@ typedef struct sPAPREnvironment {
int htab_save_index;
bool htab_first_pass;
int htab_fd;
+ bool htab_fd_stale;
} sPAPREnvironment;
#define H_SUCCESS 0
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 14/37] spapr: Fix integer overflow during migration (TCG)
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (12 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 13/37] spapr: Fix stale HTAB during live migration (KVM) Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 15/37] spapr: Fix stale HTAB during live " Alexander Graf
` (23 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, Samuel Mendoza-Jonas, qemu-devel
From: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
The n_valid and n_invalid fields are unsigned short integers but it is
possible to have more than 65535 entries in a contiguous hunk, overflowing
the field. This results in an incorrect HTAB being sent to the destination
during migration.
Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 869b721..765a44c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1065,7 +1065,7 @@ static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr,
/* Consume valid HPTEs */
chunkstart = index;
- while ((index < htabslots)
+ while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
&& HPTE_VALID(HPTE(spapr->htab, index))) {
index++;
CLEAN_HPTE(HPTE(spapr->htab, index));
@@ -1117,7 +1117,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr,
chunkstart = index;
/* Consume valid dirty HPTEs */
- while ((index < htabslots)
+ while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
&& HPTE_DIRTY(HPTE(spapr->htab, index))
&& HPTE_VALID(HPTE(spapr->htab, index))) {
CLEAN_HPTE(HPTE(spapr->htab, index));
@@ -1127,7 +1127,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr,
invalidstart = index;
/* Consume invalid dirty HPTEs */
- while ((index < htabslots)
+ while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
&& HPTE_DIRTY(HPTE(spapr->htab, index))
&& !HPTE_VALID(HPTE(spapr->htab, index))) {
CLEAN_HPTE(HPTE(spapr->htab, index));
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 15/37] spapr: Fix stale HTAB during live migration (TCG)
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (13 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 14/37] spapr: Fix integer overflow during migration (TCG) Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 16/37] device-tree: fix memory leak Alexander Graf
` (22 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, Samuel Mendoza-Jonas, qemu-devel
From: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
If a TCG guest reboots during a running migration HTAB entries are not
marked dirty, and the destination boots with an invalid HTAB.
When a reboot occurs, explicitly mark the current HTAB dirty after
clearing it.
Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 765a44c..720aab5 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -819,9 +819,16 @@ static void emulate_spapr_hypercall(PowerPCCPU *cpu)
}
}
+#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
+#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
+#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
+#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
+#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
+
static void spapr_reset_htab(sPAPREnvironment *spapr)
{
long shift;
+ int index;
/* allocate hash page table. For now we always make this 16mb,
* later we should probably make it scale to the size of guest
@@ -846,6 +853,10 @@ static void spapr_reset_htab(sPAPREnvironment *spapr)
/* And clear it */
memset(spapr->htab, 0, HTAB_SIZE(spapr));
+
+ for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) {
+ DIRTY_HPTE(HPTE(spapr->htab, index));
+ }
}
/* Update the RMA size if necessary */
@@ -1013,11 +1024,6 @@ static const VMStateDescription vmstate_spapr = {
},
};
-#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
-#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
-#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
-#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
-
static int htab_save_setup(QEMUFile *f, void *opaque)
{
sPAPREnvironment *spapr = opaque;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 16/37] device-tree: fix memory leak
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (14 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 15/37] spapr: Fix stale HTAB during live " Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 17/37] ppc: do not use get_clock_realtime() Alexander Graf
` (21 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Sergey Fedorov
From: Sergey Fedorov <serge.fdrv@gmail.com>
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
device_tree.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/device_tree.c b/device_tree.c
index df9eed9..4cb1cd5 100644
--- a/device_tree.c
+++ b/device_tree.c
@@ -324,6 +324,7 @@ int qemu_fdt_setprop_sized_cells_from_array(void *fdt,
uint64_t value;
int cellnum, vnum, ncells;
uint32_t hival;
+ int ret;
propcells = g_new0(uint32_t, numvalues * 2);
@@ -331,18 +332,23 @@ int qemu_fdt_setprop_sized_cells_from_array(void *fdt,
for (vnum = 0; vnum < numvalues; vnum++) {
ncells = values[vnum * 2];
if (ncells != 1 && ncells != 2) {
- return -1;
+ ret = -1;
+ goto out;
}
value = values[vnum * 2 + 1];
hival = cpu_to_be32(value >> 32);
if (ncells > 1) {
propcells[cellnum++] = hival;
} else if (hival != 0) {
- return -1;
+ ret = -1;
+ goto out;
}
propcells[cellnum++] = cpu_to_be32(value);
}
- return qemu_fdt_setprop(fdt, node_path, property, propcells,
- cellnum * sizeof(uint32_t));
+ ret = qemu_fdt_setprop(fdt, node_path, property, propcells,
+ cellnum * sizeof(uint32_t));
+out:
+ g_free(propcells);
+ return ret;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 17/37] ppc: do not use get_clock_realtime()
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (15 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 16/37] device-tree: fix memory leak Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 18/37] PPC: Fix crash on spapr_tce_table_finalize() Alexander Graf
` (20 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Paolo Bonzini
From: Paolo Bonzini <pbonzini@redhat.com>
Use the external qemu-timer API instead.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/ppc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index bec82cd..5ce565d 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -844,7 +844,7 @@ static void timebase_pre_save(void *opaque)
return;
}
- tb->time_of_the_day_ns = get_clock_realtime();
+ tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
/*
* tb_offset is only expected to be changed by migration so
* there is no need to update it from KVM here
@@ -873,7 +873,7 @@ static int timebase_post_load(void *opaque, int version_id)
* We try to adjust timebase by downtime if host clocks are not
* too much out of sync (1 second for now).
*/
- host_ns = get_clock_realtime();
+ host_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
ns_diff = MAX(0, host_ns - tb_remote->time_of_the_day_ns);
migration_duration_ns = MIN(NSEC_PER_SEC, ns_diff);
migration_duration_tb = muldiv64(migration_duration_ns, freq, NSEC_PER_SEC);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 18/37] PPC: Fix crash on spapr_tce_table_finalize()
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (16 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 17/37] ppc: do not use get_clock_realtime() Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 19/37] pseries: Update SLOF firmware image to 20141202 Alexander Graf
` (19 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-stable, qemu-devel, David Gibson
From: David Gibson <david@gibson.dropbear.id.au>
spapr_tce_table_finalize() can SEGV if the object was not previously
realized. In particular this can be triggered by running
qemu-system-ppc -device spapr-tce-table,?
The basic problem is that we have mismatched initialization versus
finalization: spapr_tce_table_finalize() is attempting to undo things that
are done in spapr_tce_table_realize(), not an instance_init function.
Therefore, replace spapr_tce_table_finalize() with
spapr_tce_table_unrealize().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-stable@nongnu.org
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr_iommu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c
index 6c91d8e..da47474 100644
--- a/hw/ppc/spapr_iommu.c
+++ b/hw/ppc/spapr_iommu.c
@@ -173,9 +173,9 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
return tcet;
}
-static void spapr_tce_table_finalize(Object *obj)
+static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
{
- sPAPRTCETable *tcet = SPAPR_TCE_TABLE(obj);
+ sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
QLIST_REMOVE(tcet, list);
@@ -420,6 +420,7 @@ static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->init = spapr_tce_table_realize;
dc->reset = spapr_tce_reset;
+ dc->unrealize = spapr_tce_table_unrealize;
QLIST_INIT(&spapr_tce_tables);
@@ -435,7 +436,6 @@ static TypeInfo spapr_tce_table_info = {
.parent = TYPE_DEVICE,
.instance_size = sizeof(sPAPRTCETable),
.class_init = spapr_tce_table_class_init,
- .instance_finalize = spapr_tce_table_finalize,
};
static void register_types(void)
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 19/37] pseries: Update SLOF firmware image to 20141202
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (17 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 18/37] PPC: Fix crash on spapr_tce_table_finalize() Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 20/37] target-ppc: Introduce Instruction Type for Transactional Memory Alexander Graf
` (18 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: Alexey Kardashevskiy, peter.maydell, qemu-devel
From: Alexey Kardashevskiy <aik@ozlabs.ru>
The changelog is:
> version: update to 20141202
> ipv4: Fix send packet across a subnet
> pci: scan only type 0 and type 1
> usb-xhci: support xhci extended capabilities
> Fix term-io-key to also work when stdin has not been set yet
> net-snk: llfw startup is using the wrong offset to handler
> net-snk: Make call_client_interface() a bit more ABI compliant
> net-snk: Remove custom printf version
> net-snk: Sanitize our .lds file
> net-snk: Avoid type clash for stdin & stdout
> net-snk: use socket descriptor in the network stack
> net-snk: Remove printk() in favor of printf()
> net-snk: Remove redundant prototypes
> net-snk: Remove unused timer functions
> net-snk: Remove some unused PCI functions
> net-snk: Remove module system
> net-snk: Remove insmod/rmmod
> net-snk: Remove snk_kernel_interface and related definitions
> net-snk: Remove pci/vio_config gunk
> js2x: Fix build
> net-snk: Remoe some now unused "kernel" functions
> rtas: Improve error handling in instantiate-rtas
> version: update to 20140827
> Add private HCALL to inform updated RTAS base and entry
> xhci: fix port assignment
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
pc-bios/README | 2 +-
pc-bios/slof.bin | Bin 923896 -> 911704 bytes
roms/SLOF | 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/pc-bios/README b/pc-bios/README
index edfadd7..8a85e69 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -17,7 +17,7 @@
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
https://github.com/aik/SLOF, and the image currently in qemu is
- built from git tag qemu-slof-20140630.
+ built from git tag qemu-slof-20141202.
- sgabios (the Serial Graphics Adapter option ROM) provides a means for
legacy x86 software to communicate with an attached serial console as
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 69b0a5dbc3ab423528dc10817b37fde720ffd0aa..031e3063a277e769c78b637de13c93f4074389f5 100644
GIT binary patch
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zc%#MtSnc7$|6>}snaN%f{+KDE&{G8O^YBL05zwba0{t{Vvjoa(UAeHq^l6j^oyk3@
zb6U-#L@AtB@g#dfL&E<sz&`moN)(^p3e4gEp*qIPTqv}Yjp8ZbUm~R+#%0IEl5F}O
z{8)BkIXJgs6Nglx{=_j5oSQzLH2Mt_dF*mdU;igt`ms+vW++Op68OJj^X&z|u8Y8@
z0pmpV`PIN~;YG3EP=kgqMJS|=!li-ofN#X++o=OKaJ_~K3p!R0@#okKe>y=HG&Dkd
z51Vg@LmbuP4DbyR{3esxFHOv$?Q;?BEx`UE0&fLo1Izwk`IRGo_TZ0)Zh!E{!z#Cz
z4rdd}@SkjNz46Lf!?R<*eC5@nzf?N&zK6g6o%{akz6WQPe(`T^N`9w~hs*Z%FJHOh
M`N2Q`pJ}uIA11p`>i_@%
diff --git a/roms/SLOF b/roms/SLOF
index f284ab3..a70dbda 160000
--- a/roms/SLOF
+++ b/roms/SLOF
@@ -1 +1 @@
-Subproject commit f284ab3f03ae69a20e1ae966f6ddf76da33cbf72
+Subproject commit a70dbda2e21f6e438b3617c44ff180c3418dc30f
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 20/37] target-ppc: Introduce Instruction Type for Transactional Memory
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (18 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 19/37] pseries: Update SLOF firmware image to 20141202 Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 21/37] target-ppc: Introduce Feature Flag " Alexander Graf
` (17 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Add a category (PPC2_TM) for the Transactional Memory instructions
introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 068fcb2..3510083 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2010,6 +2010,8 @@ enum {
PPC2_ISA207S = 0x0000000000008000ULL,
/* Double precision floating point conversion for signed integer 64 */
PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
+ /* Transactional Memory (ISA 2.07, Book II) */
+ PPC2_TM = 0x0000000000020000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2017,7 +2019,7 @@ enum {
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
- PPC2_FP_CVT_S64)
+ PPC2_FP_CVT_S64 | PPC2_TM)
};
/*****************************************************************************/
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 21/37] target-ppc: Introduce Feature Flag for Transactional Memory
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (19 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 20/37] target-ppc: Introduce Instruction Type for Transactional Memory Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 22/37] target-ppc: Introduce tm_enabled Bit to CPU State Alexander Graf
` (16 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Add a flag (POWERPC_FLAG_TM) for the Transactional Memory
Facility introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3510083..38176c0 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -584,6 +584,8 @@ enum {
POWERPC_FLAG_CFAR = 0x00040000,
/* Has VSX */
POWERPC_FLAG_VSX = 0x00080000,
+ /* Has Transaction Memory (ISA 2.07) */
+ POWERPC_FLAG_TM = 0x00100000,
};
/*****************************************************************************/
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 22/37] target-ppc: Introduce tm_enabled Bit to CPU State
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (20 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 21/37] target-ppc: Introduce Feature Flag " Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 23/37] target-ppc: Power8 Supports Transactional Memory Alexander Graf
` (15 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit.
This is analogous to the other "available" bits in the MSR (FP,
VSX, etc.).
NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped
with a PPC64 bit check.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a772382..3b004f3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -203,6 +203,7 @@ typedef struct DisasContext {
int altivec_enabled;
int vsx_enabled;
int spe_enabled;
+ int tm_enabled;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint64_t insns_flags;
@@ -11342,6 +11343,13 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
} else {
ctx.vsx_enabled = 0;
}
+#if defined(TARGET_PPC64)
+ if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
+ ctx.tm_enabled = msr_tm;
+ } else {
+ ctx.tm_enabled = 0;
+ }
+#endif
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
ctx.singlestep_enabled = CPU_SINGLE_STEP;
else
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 23/37] target-ppc: Power8 Supports Transactional Memory
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (21 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 22/37] target-ppc: Introduce tm_enabled Bit to CPU State Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 24/37] target-ppc: Introduce TEXASRU Bit Fields Alexander Graf
` (14 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
The Power8 processor implements the Transactional Memory Facility
as defined in Power ISA 2.07. Update the initialization code to
indicate this.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate_init.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1fece7b..72cc9d0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8219,7 +8219,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
- PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64;
+ PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+ PPC2_TM;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
@@ -8247,7 +8248,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX;
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 24/37] target-ppc: Introduce TEXASRU Bit Fields
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (22 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 23/37] target-ppc: Power8 Supports Transactional Memory Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 25/37] target-ppc: Introduce tbegin Alexander Graf
` (13 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 38176c0..91a03f6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -558,6 +558,26 @@ struct ppc_slb_t {
#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
+/* Transaction EXception And Summary Register bits */
+#define TEXASR_FAILURE_PERSISTENT (63 - 7)
+#define TEXASR_DISALLOWED (63 - 8)
+#define TEXASR_NESTING_OVERFLOW (63 - 9)
+#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
+#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
+#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
+#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
+#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
+#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
+#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
+#define TEXASR_ABORT (63 - 31)
+#define TEXASR_SUSPENDED (63 - 32)
+#define TEXASR_PRIVILEGE_HV (63 - 34)
+#define TEXASR_PRIVILEGE_PR (63 - 35)
+#define TEXASR_FAILURE_SUMMARY (63 - 36)
+#define TEXASR_TFIAR_EXACT (63 - 37)
+#define TEXASR_ROT (63 - 38)
+#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
+
enum {
POWERPC_FLAG_NONE = 0x00000000,
/* Flag for MSR bit 25 signification (VRE/SPE) */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 25/37] target-ppc: Introduce tbegin
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (23 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 24/37] target-ppc: Introduce TEXASRU Bit Fields Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 26/37] target-ppc: Introduce TM Noops Alexander Graf
` (12 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Provide a degenerate implementation of the tbegin instruction. This
implementation always fails the transaction, recording the failure
per Book II Section 5.3.2 of the Power ISA V2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/helper.h | 2 ++
target-ppc/mem_helper.c | 22 ++++++++++++++++++++++
target-ppc/translate.c | 12 ++++++++++++
3 files changed, 36 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 2841f61..869be15 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -665,3 +665,5 @@ DEF_HELPER_4(dscri, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscriq, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscli, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32)
+
+DEF_HELPER_1(tbegin, void, env)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 50344b8..6d37dae 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -269,3 +269,25 @@ STVE(stvewx, cpu_stl_data, bswap32, u32)
#undef HI_IDX
#undef LO_IDX
+
+void helper_tbegin(CPUPPCState *env)
+{
+ /* As a degenerate implementation, always fail tbegin. The reason
+ * given is "Nesting overflow". The "persistent" bit is set,
+ * providing a hint to the error handler to not retry. The TFIAR
+ * captures the address of the failure, which is this tbegin
+ * instruction. Instruction execution will continue with the
+ * next instruction in memory, which is precisely what we want.
+ */
+
+ env->spr[SPR_TEXASR] =
+ (1ULL << TEXASR_FAILURE_PERSISTENT) |
+ (1ULL << TEXASR_NESTING_OVERFLOW) |
+ (msr_hv << TEXASR_PRIVILEGE_HV) |
+ (msr_pr << TEXASR_PRIVILEGE_PR) |
+ (1ULL << TEXASR_FAILURE_SUMMARY) |
+ (1ULL << TEXASR_TFIAR_EXACT);
+ env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
+ env->spr[SPR_TFHAR] = env->nip + 4;
+ env->crf[0] = 0xB; /* 0b1010 = transaction failure */
+}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3b004f3..f4a0332 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9674,6 +9674,15 @@ GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
+static void gen_tbegin(DisasContext *ctx)
+{
+ if (unlikely(!ctx->tm_enabled)) {
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
+ return;
+ }
+ gen_helper_tbegin(cpu_env);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11086,6 +11095,9 @@ GEN_SPEOP_LDST(evstwhe, 0x18, 2),
GEN_SPEOP_LDST(evstwho, 0x1A, 2),
GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
+
+GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 26/37] target-ppc: Introduce TM Noops
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (24 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 25/37] target-ppc: Introduce tbegin Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 27/37] target-ppc: Introduce tcheck Alexander Graf
` (11 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Add degenerate implementations of the non-privileged Transactional
Memory instructions tend., tabort*. and tsr. This implementation
simply checks the MSR[TM] bit and then sets CR0 to 0b0000. This
is a reasonable degenerate implementation since transactions are
never allowed to begin and hence MSR[TS] is always 0b00.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f4a0332..9c820d1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9683,6 +9683,30 @@ static void gen_tbegin(DisasContext *ctx)
gen_helper_tbegin(cpu_env);
}
+#define GEN_TM_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->tm_enabled)) { \
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
+ return; \
+ } \
+ /* Because tbegin always fails in QEMU, these user \
+ * space instructions all have a simple implementation: \
+ * \
+ * CR[0] = 0b0 || MSR[TS] || 0b0 \
+ * = 0b0 || 0b00 || 0b0 \
+ */ \
+ tcg_gen_movi_i32(cpu_crf[0], 0); \
+}
+
+GEN_TM_NOOP(tend);
+GEN_TM_NOOP(tabort);
+GEN_TM_NOOP(tabortwc);
+GEN_TM_NOOP(tabortwci);
+GEN_TM_NOOP(tabortdc);
+GEN_TM_NOOP(tabortdci);
+GEN_TM_NOOP(tsr);
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11098,6 +11122,20 @@ GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 27/37] target-ppc: Introduce tcheck
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (25 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 26/37] target-ppc: Introduce TM Noops Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 28/37] target-ppc: Introduce Privileged TM Noops Alexander Graf
` (10 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Add a degenerate implementation of the Transaction Check (tcheck)
instruction. Since transaction always immediately fail, this
implementation simply sets CR[BF] to 0b1000, i.e. TDOOMED = 1
and MSR[TS] == 0.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9c820d1..95a2198 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9707,6 +9707,21 @@ GEN_TM_NOOP(tabortdc);
GEN_TM_NOOP(tabortdci);
GEN_TM_NOOP(tsr);
+static void gen_tcheck(DisasContext *ctx)
+{
+ if (unlikely(!ctx->tm_enabled)) {
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
+ return;
+ }
+ /* Because tbegin always fails, the tcheck implementation
+ * is simple:
+ *
+ * CR[CRF] = TDOOMED || MSR[TS] || 0b0
+ * = 0b1 || 0b00 || 0b0
+ */
+ tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11136,6 +11151,8 @@ GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
PPC_NONE, PPC2_TM),
GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 28/37] target-ppc: Introduce Privileged TM Noops
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (26 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 27/37] target-ppc: Introduce tcheck Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 29/37] PPC: e500: Fix GPIO controller interrupt number Alexander Graf
` (9 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel, Tom Musta
From: Tom Musta <tommusta@gmail.com>
Add the supervisory Transactional Memory instructions treclaim. and
trechkpt. The implementation is a degenerate one that simply
checks privileged state, TM availability and then sets CR[0] to
0b0000, just like the unprivileged noops.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 95a2198..58d7db3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9722,6 +9722,40 @@ static void gen_tcheck(DisasContext *ctx)
tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
}
+#if defined(CONFIG_USER_ONLY)
+#define GEN_TM_PRIV_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
+}
+
+#else
+
+#define GEN_TM_PRIV_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ if (unlikely(ctx->pr)) { \
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
+ return; \
+ } \
+ if (unlikely(!ctx->tm_enabled)) { \
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
+ return; \
+ } \
+ /* Because tbegin always fails, the implementation is \
+ * simple: \
+ * \
+ * CR[0] = 0b0 || MSR[TS] || 0b0 \
+ * = 0b0 || 0b00 | 0b0 \
+ */ \
+ tcg_gen_movi_i32(cpu_crf[0], 0); \
+}
+
+#endif
+
+GEN_TM_PRIV_NOOP(treclaim);
+GEN_TM_PRIV_NOOP(trechkpt);
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11153,6 +11187,10 @@ GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
PPC_NONE, PPC2_TM),
GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 29/37] PPC: e500: Fix GPIO controller interrupt number
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (27 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 28/37] target-ppc: Introduce Privileged TM Noops Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 30/37] target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY Alexander Graf
` (8 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, Amit Singh Tomar, qemu-devel
From: Amit Tomar <Amit.Tomar@freescale.com>
The GPIO controller lives at IRQ 47, not 43 on real hardware. This is a problem
because IRQ 43 is occupied by the I2C controller which we want to implement
next, so we'd have a conflict on that IRQ number.
Move the GPIO controller to IRQ 47 where it belongs.
Signed-off-by: Amit Singh Tomar <amit.tomar@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/e500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index a2e60b4..7e17d18 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -60,7 +60,7 @@
#define MPC8544_PCI_REGS_SIZE 0x1000ULL
#define MPC8544_UTIL_OFFSET 0xe0000ULL
#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
-#define MPC8XXX_GPIO_IRQ 43
+#define MPC8XXX_GPIO_IRQ 47
struct boot_info
{
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 30/37] target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (28 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 29/37] PPC: e500: Fix GPIO controller interrupt number Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 31/37] target-ppc: Cast ssize_t to size_t before printing with %zx Alexander Graf
` (7 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel
From: Peter Maydell <peter.maydell@linaro.org>
The functions SR() and gen_sync_exception() are only used in softmmu
configs; wrap them in #ifndef CONFIG_USER_ONLY to suppress clang warnings
on the linux-user builds.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
target-ppc/translate.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 58d7db3..6e9ab02 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -331,11 +331,13 @@ static inline void gen_stop_exception(DisasContext *ctx)
ctx->exception = POWERPC_EXCP_STOP;
}
+#ifndef CONFIG_USER_ONLY
/* No need to update nip here, as execution flow will change */
static inline void gen_sync_exception(DisasContext *ctx)
{
ctx->exception = POWERPC_EXCP_SYNC;
}
+#endif
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
@@ -437,7 +439,10 @@ EXTRACT_HELPER(ME, 1, 5);
EXTRACT_HELPER(TO, 21, 5);
EXTRACT_HELPER(CRM, 12, 8);
+
+#ifndef CONFIG_USER_ONLY
EXTRACT_HELPER(SR, 16, 4);
+#endif
/* mtfsf/mtfsfi */
EXTRACT_HELPER(FPBF, 23, 3);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 31/37] target-ppc: Cast ssize_t to size_t before printing with %zx
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (29 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 30/37] target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 32/37] hw/ppc: modified the condition for usb controllers to be created for some ppc machines Alexander Graf
` (6 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: peter.maydell, qemu-devel
From: Peter Maydell <peter.maydell@linaro.org>
The mingw32 compiler complains about trying to print variables of type
ssize_t with the %z format string specifier. Since we're printing it
as unsigned hex anyway, cast to size_t to silence the warning.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 720aab5..2850624 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1482,7 +1482,7 @@ static void ppc_spapr_init(MachineState *machine)
}
if (spapr->rtas_size > RTAS_MAX_SIZE) {
hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n",
- spapr->rtas_size, RTAS_MAX_SIZE);
+ (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
exit(1);
}
g_free(filename);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 32/37] hw/ppc: modified the condition for usb controllers to be created for some ppc machines
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (30 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 31/37] target-ppc: Cast ssize_t to size_t before printing with %zx Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 33/37] hw/machine: added machine_usb wrapper Alexander Graf
` (5 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: Marcel Apfelbaum, peter.maydell, qemu-devel
From: Marcel Apfelbaum <marcel@redhat.com>
Some ppc machines create a default usb controller based on a 'machine condition'.
Until now the logic was: create the usb controller if:
- the usb option was supplied in cli and value is true or
- the usb option was absent and both set_defaults and the machine
condition were true.
Modified the logic to:
Create the usb controller if:
- the machine condition is true and defaults are enabled or
- the usb option is supplied and true.
The main for this is to simplify the usb_enabled method.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/mac_newworld.c | 3 ++-
hw/ppc/spapr.c | 2 +-
include/sysemu/sysemu.h | 1 +
vl.c | 7 ++++++-
4 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index b60a832..8ba9499 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -417,7 +417,8 @@ static void ppc_core99_init(MachineState *machine)
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
- if (usb_enabled(machine_arch == ARCH_MAC99_U3)) {
+ if ((machine_arch == ARCH_MAC99_U3 && defaults_enabled()) ||
+ usb_enabled(false)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2850624..2b2cc0c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1530,7 +1530,7 @@ static void ppc_spapr_init(MachineState *machine)
spapr->has_graphics = true;
}
- if (usb_enabled(spapr->has_graphics)) {
+ if ((spapr->has_graphics && defaults_enabled()) || usb_enabled(false)) {
pci_create_simple(phb->bus, -1, "pci-ohci");
if (spapr->has_graphics) {
usbdevice_create("keyboard");
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 503e5a4..a31044c 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -227,6 +227,7 @@ void qemu_boot_set(const char *boot_order, Error **errp);
QemuOpts *qemu_get_machine_opts(void);
+bool defaults_enabled(void);
bool usb_enabled(bool default_usb);
extern QemuOptsList qemu_legacy_drive_opts;
diff --git a/vl.c b/vl.c
index bea9656..415535f 100644
--- a/vl.c
+++ b/vl.c
@@ -997,10 +997,15 @@ static int parse_name(QemuOpts *opts, void *opaque)
return 0;
}
+bool defaults_enabled(void)
+{
+ return has_defaults;
+}
+
bool usb_enabled(bool default_usb)
{
return qemu_opt_get_bool(qemu_get_machine_opts(), "usb",
- has_defaults && default_usb);
+ default_usb);
}
#ifndef _WIN32
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 33/37] hw/machine: added machine_usb wrapper
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (31 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 32/37] hw/ppc: modified the condition for usb controllers to be created for some ppc machines Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 34/37] hw/usb: simplified usb_enabled Alexander Graf
` (4 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: Marcel Apfelbaum, peter.maydell, qemu-devel
From: Marcel Apfelbaum <marcel@redhat.com>
Following QOM convention, object properties should
not be accessed directly.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/core/machine.c | 5 +++++
include/hw/boards.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index a0ae5f9..fbd91be 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -398,6 +398,11 @@ static void machine_finalize(Object *obj)
g_free(ms->firmware);
}
+bool machine_usb(MachineState *machine)
+{
+ return machine->usb;
+}
+
static const TypeInfo machine_info = {
.name = TYPE_MACHINE,
.parent = TYPE_OBJECT,
diff --git a/include/hw/boards.h b/include/hw/boards.h
index e0a6790..3ddc449 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -65,6 +65,8 @@ int qemu_register_machine(QEMUMachine *m);
MachineClass *find_default_machine(void);
extern MachineState *current_machine;
+bool machine_usb(MachineState *machine);
+
/**
* MachineClass:
* @qemu_machine: #QEMUMachine
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 34/37] hw/usb: simplified usb_enabled
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (32 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 33/37] hw/machine: added machine_usb wrapper Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 35/37] hw/ppc/mac_newworld: QOMified mac99 machines Alexander Graf
` (3 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: Marcel Apfelbaum, peter.maydell, qemu-devel
From: Marcel Apfelbaum <marcel@redhat.com>
The argument is not longer used and the implementation
uses now QOM instead of QemuOpts.
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/arm/nseries.c | 2 +-
hw/arm/pxa2xx.c | 4 ++--
hw/arm/realview.c | 2 +-
hw/arm/versatilepb.c | 2 +-
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
hw/ppc/mac_newworld.c | 2 +-
hw/ppc/mac_oldworld.c | 2 +-
hw/ppc/prep.c | 2 +-
hw/ppc/spapr.c | 2 +-
include/sysemu/sysemu.h | 2 +-
vl.c | 11 +++++------
12 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index c7ebaa6..4d7be5e 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -1344,7 +1344,7 @@ static void n8x0_init(MachineState *machine,
n8x0_dss_setup(s);
n8x0_cbus_setup(s);
n8x0_uart_setup(s);
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
n8x0_usb_setup(s);
}
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 8967cc4..165ba2a 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -2143,7 +2143,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
sysbus_create_simple("sysbus-ohci", 0x4c000000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
}
@@ -2276,7 +2276,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
sysbus_create_simple("sysbus-ohci", 0x4c000000,
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
}
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 66e51ef..50cb93d 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -261,7 +261,7 @@ static void realview_init(MachineState *machine,
sysbus_connect_irq(busdev, 2, pic[50]);
sysbus_connect_irq(busdev, 3, pic[51]);
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
n = drive_get_max_bus(IF_SCSI);
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 6c4c2e7..b1dae77 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -281,7 +281,7 @@ static void versatile_init(MachineState *machine, int board_id)
pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
}
}
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
n = drive_get_max_bus(IF_SCSI);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 220f741..f0a3201 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -274,7 +274,7 @@ static void pc_init1(MachineState *machine,
pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order,
machine, floppy, idebus[0], idebus[1], rtc_state);
- if (pci_enabled && usb_enabled(false)) {
+ if (pci_enabled && usb_enabled()) {
pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 7ba0535..a432944 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -265,7 +265,7 @@ static void pc_q35_init(MachineState *machine)
ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
ahci_ide_create_devs(ahci, hd);
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
/* Should we create 6 UHCI according to ich9 spec? */
ehci_create_ich9_with_companions(host_bus, 0x1d);
}
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 8ba9499..ed37d6b 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -418,7 +418,7 @@ static void ppc_core99_init(MachineState *machine)
qdev_init_nofail(dev);
if ((machine_arch == ARCH_MAC99_U3 && defaults_enabled()) ||
- usb_enabled(false)) {
+ usb_enabled()) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index c7224d7..3079510 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -304,7 +304,7 @@ static void ppc_heathrow_init(MachineState *machine)
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index dd8433d..15df7f3 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -539,7 +539,7 @@ static void ppc_prep_init(MachineState *machine)
memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
#endif
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2b2cc0c..d2b8b12 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1530,7 +1530,7 @@ static void ppc_spapr_init(MachineState *machine)
spapr->has_graphics = true;
}
- if ((spapr->has_graphics && defaults_enabled()) || usb_enabled(false)) {
+ if ((spapr->has_graphics && defaults_enabled()) || usb_enabled()) {
pci_create_simple(phb->bus, -1, "pci-ohci");
if (spapr->has_graphics) {
usbdevice_create("keyboard");
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index a31044c..748d059 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -228,7 +228,7 @@ void qemu_boot_set(const char *boot_order, Error **errp);
QemuOpts *qemu_get_machine_opts(void);
bool defaults_enabled(void);
-bool usb_enabled(bool default_usb);
+bool usb_enabled(void);
extern QemuOptsList qemu_legacy_drive_opts;
extern QemuOptsList qemu_common_drive_opts;
diff --git a/vl.c b/vl.c
index 415535f..7786b2f 100644
--- a/vl.c
+++ b/vl.c
@@ -1002,10 +1002,9 @@ bool defaults_enabled(void)
return has_defaults;
}
-bool usb_enabled(bool default_usb)
+bool usb_enabled(void)
{
- return qemu_opt_get_bool(qemu_get_machine_opts(), "usb",
- default_usb);
+ return machine_usb(current_machine);
}
#ifndef _WIN32
@@ -1229,7 +1228,7 @@ static int usb_device_add(const char *devname)
const char *p;
#endif
- if (!usb_enabled(false)) {
+ if (!usb_enabled()) {
return -1;
}
@@ -1261,7 +1260,7 @@ static int usb_device_del(const char *devname)
return -1;
}
- if (!usb_enabled(false)) {
+ if (!usb_enabled()) {
return -1;
}
@@ -4230,7 +4229,7 @@ int main(int argc, char **argv, char **envp)
set_numa_modes();
/* init USB devices */
- if (usb_enabled(false)) {
+ if (usb_enabled()) {
if (foreach_device_config(DEV_USB, usb_parse) < 0)
exit(1);
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 35/37] hw/ppc/mac_newworld: QOMified mac99 machines
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (33 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 34/37] hw/usb: simplified usb_enabled Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 36/37] hw/ppc/spapr: simplify usb controller creation logic Alexander Graf
` (2 subsequent siblings)
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: Marcel Apfelbaum, peter.maydell, qemu-devel
From: Marcel Apfelbaum <marcel@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/mac_newworld.c | 29 +++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index ed37d6b..b54f94a 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -502,18 +502,27 @@ static int core99_kvm_type(const char *arg)
return 2;
}
-static QEMUMachine core99_machine = {
- .name = "mac99",
- .desc = "Mac99 based PowerMAC",
- .init = ppc_core99_init,
- .max_cpus = MAX_CPUS,
- .default_boot_order = "cd",
- .kvm_type = core99_kvm_type,
+static void core99_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->name = "mac99";
+ mc->desc = "Mac99 based PowerMAC";
+ mc->init = ppc_core99_init;
+ mc->max_cpus = MAX_CPUS;
+ mc->default_boot_order = "cd";
+ mc->kvm_type = core99_kvm_type;
+}
+
+static const TypeInfo core99_machine_info = {
+ .name = "mac99-machine",
+ .parent = TYPE_MACHINE,
+ .class_init = core99_machine_class_init,
};
-static void core99_machine_init(void)
+static void mac_machine_register_types(void)
{
- qemu_register_machine(&core99_machine);
+ type_register_static(&core99_machine_info);
}
-machine_init(core99_machine_init);
+type_init(mac_machine_register_types)
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 36/37] hw/ppc/spapr: simplify usb controller creation logic
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (34 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 35/37] hw/ppc/mac_newworld: QOMified mac99 machines Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-07 15:20 ` [Qemu-devel] [PULL 37/37] hw/ppc/mac_newworld: " Alexander Graf
2015-01-10 21:02 ` [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Peter Maydell
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: Marcel Apfelbaum, peter.maydell, qemu-devel
From: Marcel Apfelbaum <marcel@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/spapr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d2b8b12..b560459 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1528,9 +1528,10 @@ static void ppc_spapr_init(MachineState *machine)
/* Graphics */
if (spapr_vga_init(phb->bus)) {
spapr->has_graphics = true;
+ machine->usb |= defaults_enabled();
}
- if ((spapr->has_graphics && defaults_enabled()) || usb_enabled()) {
+ if (machine->usb) {
pci_create_simple(phb->bus, -1, "pci-ohci");
if (spapr->has_graphics) {
usbdevice_create("keyboard");
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PULL 37/37] hw/ppc/mac_newworld: simplify usb controller creation logic
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (35 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 36/37] hw/ppc/spapr: simplify usb controller creation logic Alexander Graf
@ 2015-01-07 15:20 ` Alexander Graf
2015-01-10 21:02 ` [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Peter Maydell
37 siblings, 0 replies; 42+ messages in thread
From: Alexander Graf @ 2015-01-07 15:20 UTC (permalink / raw)
To: qemu-ppc; +Cc: Marcel Apfelbaum, peter.maydell, qemu-devel
From: Marcel Apfelbaum <marcel@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ppc/mac_newworld.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index b54f94a..c377012 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -371,6 +371,7 @@ static void ppc_core99_init(MachineState *machine)
/* 970 gets a U3 bus */
pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
machine_arch = ARCH_MAC99_U3;
+ machine->usb |= defaults_enabled();
} else {
pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
machine_arch = ARCH_MAC99;
@@ -417,8 +418,7 @@ static void ppc_core99_init(MachineState *machine)
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
- if ((machine_arch == ARCH_MAC99_U3 && defaults_enabled()) ||
- usb_enabled()) {
+ if (machine->usb) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07
2015-01-07 15:20 [Qemu-devel] [PULL 00/37] ppc patch queue 2015-01-07 Alexander Graf
` (36 preceding siblings ...)
2015-01-07 15:20 ` [Qemu-devel] [PULL 37/37] hw/ppc/mac_newworld: " Alexander Graf
@ 2015-01-10 21:02 ` Peter Maydell
37 siblings, 0 replies; 42+ messages in thread
From: Peter Maydell @ 2015-01-10 21:02 UTC (permalink / raw)
To: Alexander Graf; +Cc: qemu-ppc@nongnu.org, QEMU Developers
On 7 January 2015 at 15:20, Alexander Graf <agraf@suse.de> wrote:
> Hi Peter,
>
> This is my current patch queue for ppc. Please pull.
>
> Alex
>
>
> The following changes since commit ab0302ee764fd702465aef6d88612cdff4302809:
>
> Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20141223' into staging (2014-12-23 15:05:22 +0000)
>
> are available in the git repository at:
>
>
> git://github.com/agraf/qemu.git tags/signed-ppc-for-upstream
>
> for you to fetch changes up to 75c74ccbe1d4175edb79c6f810c2207dcf5edb22:
>
> hw/ppc/mac_newworld: simplify usb controller creation logic (2015-01-07 16:16:29 +0100)
>
> ----------------------------------------------------------------
> Patch queue for ppc - 2015-01-07
>
> New year's release. This time's highlights:
>
> - E500: More RAM support
> - pseries: New SLOF release
> - Migration fixes
> - Simplify USB spawning logic, removes support for explicit usb=off
> - TCG: Simple untansactional TM emulation
>
> ----------------------------------------------------------------
Applied, thanks. (I'd already applied the USB fixes earlier, but the merge
seems to have worked smoothly.)
-- PMM
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