From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8sPn-0005tS-PZ for qemu-devel@nongnu.org; Wed, 07 Jan 2015 10:21:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y8sPj-0003Ba-4i for qemu-devel@nongnu.org; Wed, 07 Jan 2015 10:20:55 -0500 From: Alexander Graf Date: Wed, 7 Jan 2015 16:20:19 +0100 Message-Id: <1420644048-16919-9-git-send-email-agraf@suse.de> In-Reply-To: <1420644048-16919-1-git-send-email-agraf@suse.de> References: <1420644048-16919-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 08/37] target-ppc: mffs. Should Set CR1 from FPSCR Bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Tom Musta From: Tom Musta Update the Move From FPSCR (mffs.) instruction to correctly set CR[1] from FPSCR[FX,FEX,VX,OX]. Signed-off-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 35c3a16..32c9f49 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2504,7 +2504,9 @@ static void gen_mffs(DisasContext *ctx) } gen_reset_fpstatus(); tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); - gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); + if (unlikely(Rc(ctx->opcode))) { + gen_set_cr1_from_fpscr(ctx); + } } /* mtfsb0 */ -- 1.8.1.4