From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44065) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDJvC-0002lp-2Q for qemu-devel@nongnu.org; Mon, 19 Jan 2015 16:31:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YDJvA-0007nN-V5 for qemu-devel@nongnu.org; Mon, 19 Jan 2015 16:31:42 -0500 Received: from smtp2-g21.free.fr ([2a01:e0c:1:1599::11]:26730) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDJvA-0007nA-Pw for qemu-devel@nongnu.org; Mon, 19 Jan 2015 16:31:40 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 19 Jan 2015 22:28:36 +0100 Message-Id: <1421702918-27143-7-git-send-email-hpoussin@reactos.org> In-Reply-To: <1421702918-27143-1-git-send-email-hpoussin@reactos.org> References: <1421702918-27143-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 6/7] gt64xxx: remove isa_mem_base usage List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Leon Alrae , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno Create a custom address space for PCI memory region and use it for the PC= I bus. However, continue to hardcode VGA window address at 0x10000000 instead of calculating its address dynamically. Signed-off-by: Herv=C3=A9 Poussineau --- I would be quite happy if someone knowing gt64xxx better than me can prov= ide a better patch. --- hw/mips/gt64xxx_pci.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 1f2fe5f..eb323cb 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -240,6 +240,9 @@ typedef struct GT64120State { uint32_t regs[GT_REGS]; PCI_MAPPING_ENTRY(PCI0IO); PCI_MAPPING_ENTRY(ISD); + MemoryRegion pci0_mem; + MemoryRegion vga_window; + AddressSpace pci0_mem_as; } GT64120State; =20 /* Adjust range to avoid touching space which isn't mappable via PCI */ @@ -302,7 +305,6 @@ static void gt64120_pci_mapping(GT64120State *s) /* Map new IO address */ s->PCI0IO_start =3D s->regs[GT_PCI0IOLD] << 21; s->PCI0IO_length =3D ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI= 0IOLD] & 0x7f)) << 21; - isa_mem_base =3D s->PCI0IO_start; if (s->PCI0IO_length) { memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio"= , get_system_io(), 0, s->PCI0IO_length)= ; @@ -1124,10 +1126,16 @@ PCIBus *gt64120_register(qemu_irq *pic) qdev_init_nofail(dev); d =3D GT64120_PCI_HOST_BRIDGE(dev); phb =3D PCI_HOST_BRIDGE(dev); + memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX= ); + address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); + memory_region_init_alias(&d->vga_window, OBJECT(dev), "vga", + &d->pci0_mem, 0xa0000, QEMU_PCI_VGA_MEM_SIZ= E); + memory_region_add_subregion_overlap(get_system_memory(), 0x10000000, + &d->vga_window, 1); phb->bus =3D pci_register_bus(dev, "pci", gt64120_pci_set_irq, gt64120_pci_map_irq= , pic, - get_system_memory(), + &d->pci0_mem, get_system_io(), PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "is= d-mem", 0x1000); @@ -1142,11 +1150,6 @@ static int gt64120_init(SysBusDevice *dev) =20 s =3D GT64120_PCI_HOST_BRIDGE(dev); =20 - /* FIXME: This value is computed from registers during reset, but so= me - devices (e.g. VGA card) need to know it when they are registered. - This also mean that changing the register to change the mapping - does not fully work. */ - isa_mem_base =3D 0x10000000; qemu_register_reset(gt64120_reset, s); return 0; } --=20 1.7.10.4