From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDKOz-00064t-Lk for qemu-devel@nongnu.org; Mon, 19 Jan 2015 17:02:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YDKOt-0000XN-Se for qemu-devel@nongnu.org; Mon, 19 Jan 2015 17:02:29 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Mon, 19 Jan 2015 22:59:31 +0100 Message-Id: <1421704772-10394-4-git-send-email-hpoussin@reactos.org> In-Reply-To: <1421704772-10394-1-git-send-email-hpoussin@reactos.org> References: <1421704772-10394-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 3/4] m48t59: add a Nvram interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Mark Cave-Ayland , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Signed-off-by: Herv=C3=A9 Poussineau --- hw/timer/m48t59.c | 59 +++++++++++++++++++++++++++++++++++++++= ++++++ include/hw/timer/m48t59.h | 24 ++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index c46b63c..c5e74ce 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -798,6 +798,24 @@ static int m48t59_init1(SysBusDevice *dev) return 0; } =20 +static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) +{ + M48txxISAState *d =3D M48TXX_ISA(obj); + return m48t59_read(&d->state, addr); +} + +static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) +{ + M48txxISAState *d =3D M48TXX_ISA(obj); + m48t59_write(&d->state, addr, val); +} + +static void m48txx_isa_toggle_lock(Nvram *obj, int lock) +{ + M48txxISAState *d =3D M48TXX_ISA(obj); + m48t59_toggle_lock(&d->state, lock); +} + static Property m48t59_isa_properties[] =3D { DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), DEFINE_PROP_END_OF_LIST(), @@ -806,10 +824,14 @@ static Property m48t59_isa_properties[] =3D { static void m48txx_isa_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + NvramClass *nc =3D NVRAM_CLASS(klass); =20 dc->realize =3D m48t59_isa_realize; dc->reset =3D m48t59_reset_isa; dc->props =3D m48t59_isa_properties; + nc->read =3D m48txx_isa_read; + nc->write =3D m48txx_isa_write; + nc->toggle_lock =3D m48txx_isa_toggle_lock; } =20 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *dat= a) @@ -820,13 +842,35 @@ static void m48txx_isa_concrete_class_init(ObjectCl= ass *klass, void *data) u->info =3D *info; } =20 +static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr) +{ + M48txxSysBusState *d =3D M48TXX_SYS_BUS(obj); + return m48t59_read(&d->state, addr); +} + +static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val) +{ + M48txxSysBusState *d =3D M48TXX_SYS_BUS(obj); + m48t59_write(&d->state, addr, val); +} + +static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock) +{ + M48txxSysBusState *d =3D M48TXX_SYS_BUS(obj); + m48t59_toggle_lock(&d->state, lock); +} + static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); + NvramClass *nc =3D NVRAM_CLASS(klass); =20 k->init =3D m48t59_init1; dc->reset =3D m48t59_reset_sysbus; + nc->read =3D m48txx_sysbus_read; + nc->write =3D m48txx_sysbus_write; + nc->toggle_lock =3D m48txx_sysbus_toggle_lock; } =20 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *= data) @@ -837,12 +881,22 @@ static void m48txx_sysbus_concrete_class_init(Objec= tClass *klass, void *data) u->info =3D *info; } =20 +static const TypeInfo nvram_info =3D { + .name =3D TYPE_NVRAM, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(NvramClass), +}; + static const TypeInfo m48txx_sysbus_type_info =3D { .name =3D TYPE_M48TXX_SYS_BUS, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(M48txxSysBusState), .abstract =3D true, .class_init =3D m48txx_sysbus_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_NVRAM }, + { } + } }; =20 static const TypeInfo m48txx_isa_type_info =3D { @@ -851,6 +905,10 @@ static const TypeInfo m48txx_isa_type_info =3D { .instance_size =3D sizeof(M48txxISAState), .abstract =3D true, .class_init =3D m48txx_isa_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_NVRAM }, + { } + } }; =20 static void m48t59_register_types(void) @@ -867,6 +925,7 @@ static void m48t59_register_types(void) }; int i; =20 + type_register_static(&nvram_info); type_register_static(&m48txx_sysbus_type_info); type_register_static(&m48txx_isa_type_info); =20 diff --git a/include/hw/timer/m48t59.h b/include/hw/timer/m48t59.h index 8217522..ddbbda2 100644 --- a/include/hw/timer/m48t59.h +++ b/include/hw/timer/m48t59.h @@ -1,6 +1,9 @@ #ifndef NVRAM_H #define NVRAM_H =20 +#include "qemu-common.h" +#include "qom/object.h" + /* NVRAM helpers */ typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr); typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val= ); @@ -34,4 +37,25 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_= base, uint16_t size, M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, uint32_t io_base, uint16_t size, int type); =20 +#define TYPE_NVRAM "nvram" + +#define NVRAM_CLASS(klass) \ + OBJECT_CLASS_CHECK(NvramClass, (klass), TYPE_NVRAM) +#define NVRAM_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NvramClass, (obj), TYPE_NVRAM) +#define NVRAM(obj) \ + INTERFACE_CHECK(Nvram, (obj), TYPE_NVRAM) + +typedef struct Nvram { + Object parent; +} Nvram; + +typedef struct NvramClass { + InterfaceClass parent; + + uint32_t (*read)(Nvram *obj, uint32_t addr); + void (*write)(Nvram *obj, uint32_t addr, uint32_t val); + void (*toggle_lock)(Nvram *obj, int lock); +} NvramClass; + #endif /* !NVRAM_H */ --=20 1.7.10.4