From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YENov-0001k0-Bh for qemu-devel@nongnu.org; Thu, 22 Jan 2015 14:53:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YENop-0007zU-4M for qemu-devel@nongnu.org; Thu, 22 Jan 2015 14:53:37 -0500 From: Marcel Apfelbaum Date: Thu, 22 Jan 2015 21:52:31 +0200 Message-Id: <1421956363-23502-6-git-send-email-marcel@redhat.com> In-Reply-To: <1421956363-23502-1-git-send-email-marcel@redhat.com> References: <1421956363-23502-1-git-send-email-marcel@redhat.com> Subject: [Qemu-devel] [PATCH RFC 05/17] hw/acpi: remove from root bus 0 the crs resources used by other busses. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: seabios@seabios.org, kraxel@redhat.com, mst@redhat.com, quintela@redhat.com, agraf@suse.de, alex.williamson@redhat.com, kevin@koconnor.net, qemu-ppc@nongnu.org, hare@suse.de, imammedo@redhat.com, amit.shah@redhat.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net If multiple root busses are used, root bus 0 cannot use all the pci holes ranges. Remove the IO/mem ranges used by the other primary busses. todo: properly compute the bus ranges for root bus 0. Signed-off-by: Marcel Apfelbaum --- hw/i386/acpi-build.c | 74 +++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 62 insertions(+), 12 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 740254a..8a91e96 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -834,6 +834,8 @@ build_ssdt(AcpiAml *table_aml, GArray *linker, int i; PciMemoryRangeQ io_ranges = QLIST_HEAD_INITIALIZER(io_ranges); PciMemoryRangeQ mem_ranges = QLIST_HEAD_INITIALIZER(mem_ranges); + PciMemoryRange range; + PciMemoryRangeEntry *entry; /* The current AML generator can cover the APIC ID range [0..255], * inclusive, for VCPU hotplug. */ @@ -873,8 +875,6 @@ build_ssdt(AcpiAml *table_aml, GArray *linker, aml_append(&ssdt, scope); } - pci_mem_range_list_free(&io_ranges); - pci_mem_range_list_free(&mem_ranges); qapi_free_PciInfoList(info_list); } @@ -883,26 +883,73 @@ build_ssdt(AcpiAml *table_aml, GArray *linker, crs = acpi_resource_template(); aml_append(&crs, acpi_word_bus_number(acpi_min_fixed, acpi_max_fixed, acpi_pos_decode, - 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); + 0x0000, 0x0000, 0x0001, 0x0000, 0x0002)); aml_append(&crs, acpi_io(acpi_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); aml_append(&crs, acpi_word_io(acpi_min_fixed, acpi_max_fixed, acpi_pos_decode, acpi_entire_range, 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); - aml_append(&crs, - acpi_word_io(acpi_min_fixed, acpi_max_fixed, - acpi_pos_decode, acpi_entire_range, - 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); + + /* prepare PCI IO ranges */ + range.base = 0x0D00; + range.limit = 0xFFFF; + if (QLIST_EMPTY(&io_ranges)) { + aml_append(&crs, + acpi_word_io(acpi_min_fixed, acpi_max_fixed, + acpi_pos_decode, acpi_entire_range, + 0x0000, range.base, range.limit, + 0x0000, range.limit - range.base + 1)); + } else { + QLIST_FOREACH(entry, &io_ranges, entry) { + aml_append(&crs, + acpi_word_io(acpi_min_fixed, acpi_max_fixed, + acpi_pos_decode, acpi_entire_range, + 0x0000, range.base, entry->range.base - 1, + 0x0000, entry->range.base - range.base)); + range.base = entry->range.limit + 1; + if (!QLIST_NEXT(entry, entry)) { + aml_append(&crs, + acpi_word_io(acpi_min_fixed, acpi_max_fixed, + acpi_pos_decode, acpi_entire_range, + 0x0000, range.base, range.limit, + 0x0000, range.limit - range.base + 1)); + } + } + } + aml_append(&crs, acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed, acpi_cacheable, acpi_ReadWrite, 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); - aml_append(&crs, - acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed, - acpi_non_cacheable, acpi_ReadWrite, - 0, pci->w32.begin, pci->w32.end - 1, 0, - pci->w32.end - pci->w32.begin)); + + /* prepare PCI memory ranges */ + range.base = pci->w32.begin; + range.limit = pci->w32.end - 1; + if (QLIST_EMPTY(&mem_ranges)) { + aml_append(&crs, + acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed, + acpi_non_cacheable, acpi_ReadWrite, + 0, range.base, range.limit, 0, + range.limit - range.base + 1)); + } else { + QLIST_FOREACH(entry, &mem_ranges, entry) { + aml_append(&crs, + acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed, + acpi_non_cacheable, acpi_ReadWrite, + 0, range.base, entry->range.base - 1, + 0, entry->range.base - range.base)); + range.base = entry->range.limit + 1; + if (!QLIST_NEXT(entry, entry)) { + aml_append(&crs, + acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed, + acpi_non_cacheable, acpi_ReadWrite, + 0, range.base, range.limit, + 0, range.base - range.limit + 1)); + } + } + } + if (pci->w64.begin) { aml_append(&crs, acpi_qword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed, @@ -912,6 +959,9 @@ build_ssdt(AcpiAml *table_aml, GArray *linker, } aml_append(&scope, acpi_name_decl("_CRS", crs)); + pci_mem_range_list_free(&io_ranges); + pci_mem_range_list_free(&mem_ranges); + /* reserve PCIHP resources */ if (pm->pcihp_io_len) { dev = acpi_device("PHPR"); -- 2.1.0