From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYL-0000Fi-6A for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEfYG-0005Ge-Iu for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:41 -0500 Received: from mail-pa0-f53.google.com ([209.85.220.53]:41831) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYG-0005GY-Dt for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:36 -0500 Received: by mail-pa0-f53.google.com with SMTP id kx10so6215739pab.12 for ; Fri, 23 Jan 2015 06:49:35 -0800 (PST) From: Greg Bellows Date: Fri, 23 Jan 2015 08:49:20 -0600 Message-Id: <1422024563-27096-2-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> References: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH 1/4] target-arm: Fix RVBAR_EL1 register encoding List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Greg Bellows Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1 Signed-off-by: Greg Bellows --- target-arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1a5e067..c9b1c08 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3055,7 +3055,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; ARMCPRegInfo rvbar = { .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar }; define_one_arm_cp_reg(cpu, &rvbar); -- 1.8.3.2