From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYM-0000H5-GH for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEfYJ-0005Hl-B9 for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:42 -0500 Received: from mail-pa0-f42.google.com ([209.85.220.42]:50641) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYJ-0005HE-1P for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:39 -0500 Received: by mail-pa0-f42.google.com with SMTP id bj1so8029495pad.1 for ; Fri, 23 Jan 2015 06:49:38 -0800 (PST) From: Greg Bellows Date: Fri, 23 Jan 2015 08:49:22 -0600 Message-Id: <1422024563-27096-4-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> References: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH 3/4] target-arm: Change reset to highest available EL List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Greg Bellows Update to arm_cpu_reset() to reset into the highest available exception level based on the set ARM features. Signed-off-by: Greg Bellows --- hw/arm/boot.c | 10 ++++++++++ target-arm/cpu.c | 10 +++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 52ebd8b..148011b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -464,6 +464,16 @@ static void do_cpu_reset(void *opaque) * requested. */ if (arm_feature(env, ARM_FEATURE_EL3) && !info->secure_boot) { + /* AArch64 is defined to come out of reset into EL3 if enabled. + * If we are booting Linux then we need to adjust our EL as + * Linux expects us to be EL1. AArch32 resets into SVC, which + * Linux expects, so no privilege/exception level to adjust. + */ + if (env->aarch64) { + env->pstate = PSTATE_MODE_EL1h; + } + + /* Linux expects non-secure state */ env->cp15.scr_el3 |= SCR_NS; } diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 285947f..6793596 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -113,7 +113,15 @@ static void arm_cpu_reset(CPUState *s) /* and to the FP/Neon instructions */ env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); #else - env->pstate = PSTATE_MODE_EL1h; + /* Reset into the highest available EL */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + env->pstate = PSTATE_MODE_EL3h; + env->cp15.scr_el3 &= ~SCR_NS; + } else if (arm_feature(env, ARM_FEATURE_EL3)) { + env->pstate = PSTATE_MODE_EL2h; + } else { + env->pstate = PSTATE_MODE_EL1h; + } env->pc = cpu->rvbar; #endif } else { -- 1.8.3.2