From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYO-0000La-Fq for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEfYK-0005Iu-Mi for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:44 -0500 Received: from mail-pd0-f171.google.com ([209.85.192.171]:35282) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYK-0005Ia-Hn for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:40 -0500 Received: by mail-pd0-f171.google.com with SMTP id fp1so8934558pdb.2 for ; Fri, 23 Jan 2015 06:49:40 -0800 (PST) From: Greg Bellows Date: Fri, 23 Jan 2015 08:49:23 -0600 Message-Id: <1422024563-27096-5-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> References: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH 4/4] target-arm: Add missing SP_ELx register definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Greg Bellows Added CP register definitions for SP_EL1 and SP_EL2. Signed-off-by: Greg Bellows --- target-arm/helper.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index d5f0997..ae7394d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2096,7 +2096,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) return cpu->dcz_blocksize | dzp_bit; } -static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) +static CPAccessResult sp_el_access(CPUARMState *env, const ARMCPRegInfo *ri) { if (!(env->pstate & PSTATE_SP)) { /* Access to SP_EL0 is undefined if it's being used as @@ -2326,9 +2326,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { */ { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, - .access = PL1_RW, .accessfn = sp_el0_access, + .access = PL1_RW, .accessfn = sp_el_access, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL2_RW, .accessfn = sp_el_access, + .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_MIGRATE, @@ -2410,6 +2415,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), .resetvalue = 0 }, + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL3_RW, .accessfn = sp_el_access, + .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, REGINFO_SENTINEL }; -- 1.8.3.2