From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEiqb-0002f8-1Y for qemu-devel@nongnu.org; Fri, 23 Jan 2015 13:20:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEiqa-0000y4-6Y for qemu-devel@nongnu.org; Fri, 23 Jan 2015 13:20:44 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54980) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEiqa-0000ph-18 for qemu-devel@nongnu.org; Fri, 23 Jan 2015 13:20:44 -0500 From: Peter Maydell Date: Fri, 23 Jan 2015 18:20:20 +0000 Message-Id: <1422037228-5363-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1422037228-5363-1-git-send-email-peter.maydell@linaro.org> References: <1422037228-5363-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 03/11] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Andrew Jones , Greg Bellows , =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org The LDT/STT (load/store unprivileged) instruction decode was using the wrong MMU index value. This meant that instead of these insns being "always access as if user-mode regardless of current privilege" they were "always access as if kernel-mode regardless of current privilege". This went unnoticed because AArch64 Linux doesn't use these instructions. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell --- I'm not counting this as a security issue because I'm assuming nobody treats TCG guests as a security boundary (certainly I would not recommend doing so...) --- target-arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 80d2359..dac2f63 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -2107,7 +2107,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn) } } else { TCGv_i64 tcg_rt = cpu_reg(s, rt); - int memidx = is_unpriv ? 1 : get_mem_index(s); + int memidx = is_unpriv ? MMU_USER_IDX : get_mem_index(s); if (is_store) { do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx); -- 1.9.1