From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40750) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFlbO-0005h2-KH for qemu-devel@nongnu.org; Mon, 26 Jan 2015 10:29:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YFlb8-0000Mh-KY for qemu-devel@nongnu.org; Mon, 26 Jan 2015 10:29:22 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:59350) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFlb8-0000Li-EZ for qemu-devel@nongnu.org; Mon, 26 Jan 2015 10:29:06 -0500 From: Bastian Koppelmann Date: Mon, 26 Jan 2015 16:29:56 +0000 Message-Id: <1422289800-22812-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v2 0/4] TriCore add instructions of RR1, RR2, RRPW and RRR opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net Hi, this is a rather short patchset, that only implements instructions of four formats. There will be another patchset, which has a few bugfixes. Cheers, Bastian v1 -> v2: - Add 3 helper functions (gen_mul_q, gen_mul_q_16, gen_mulr_q) to remove repetition. - gen_mul_q now uses 64 arithmetic instead of emulating it. - MUL_Q now uses arithmetic shift, instead of normal shift + sign extend for arg extraction. - optimize OPC2_32_RRPW_EXTR by using only two shifts, instead of four. - OPC1_32_RRPW_DEXTR now has r1 == r2 as a special case. Bastian Koppelmann (4): target-tricore: target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode target-tricore: Add instructions of RR2 opcode format target-tricore: Add instructions of RRPW opcode format target-tricore: Add instructions of RRR opcode format target-tricore/helper.h | 8 + target-tricore/op_helper.c | 160 ++++++++++++++ target-tricore/translate.c | 439 +++++++++++++++++++++++++++++++++++++++ target-tricore/tricore-opcodes.h | 2 +- 4 files changed, 608 insertions(+), 1 deletion(-) -- 2.2.2