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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL v2 1/9] target-tricore: Add missing ULL suffix on 64 bit constant
Date: Tue, 27 Jan 2015 12:09:17 +0000	[thread overview]
Message-ID: <1422360565-15503-2-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1422360565-15503-1-git-send-email-kbastian@mail.uni-paderborn.de>

From: Peter Maydell <peter.maydell@linaro.org>

Add a missing ULL suffix to a 64 bit constant: this suppresses a
compiler warning from mingw32 gcc.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/op_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 13e2729..5704549 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -994,7 +994,7 @@ uint32_t helper_sha(CPUTriCoreState *env, target_ulong r1, target_ulong r2)
     } else if (shift_count > 0) {
         result = t1 << shift_count;
         /* calc carry */
-        env->PSW_USB_C = ((result & 0xffffffff00000000) != 0);
+        env->PSW_USB_C = ((result & 0xffffffff00000000ULL) != 0);
         /* calc v */
         env->PSW_USB_V = (((result > 0x7fffffffLL) ||
                            (result < -0x80000000LL)) << 31);
-- 
2.2.2

  reply	other threads:[~2015-01-27 11:08 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-27 12:09 [Qemu-devel] [PULL v2 0/9] tricore patches Bastian Koppelmann
2015-01-27 12:09 ` Bastian Koppelmann [this message]
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 2/9] target-tricore: Several translator and cpu model fixes Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 3/9] target-tricore: calculate av bits before saturation Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 4/9] target-tricore: Fix bugs found by coverity Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 5/9] target-tricore: split up suov32 into suov32_pos and suov32_neg Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 6/9] target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 7/9] target-tricore: Add instructions of RR2 opcode format Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 8/9] target-tricore: Add instructions of RRPW " Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 9/9] target-tricore: Add instructions of RRR " Bastian Koppelmann
2015-01-27 12:47 ` [Qemu-devel] [PULL v2 0/9] tricore patches Peter Maydell

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