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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL v2 7/9] target-tricore: Add instructions of RR2 opcode format
Date: Tue, 27 Jan 2015 12:09:23 +0000	[thread overview]
Message-ID: <1422360565-15503-8-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1422360565-15503-1-git-send-email-kbastian@mail.uni-paderborn.de>

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-tricore/translate.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 5e9eb28..ea0a2fc 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -4958,6 +4958,39 @@ static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
     tcg_temp_free(temp2);
 }
 
+/* RR2 format */
+static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
+{
+    uint32_t op2;
+    int r1, r2, r3;
+
+    op2 = MASK_OP_RR2_OP2(ctx->opcode);
+    r1  = MASK_OP_RR2_S1(ctx->opcode);
+    r2  = MASK_OP_RR2_S2(ctx->opcode);
+    r3  = MASK_OP_RR2_D(ctx->opcode);
+    switch (op2) {
+    case OPC2_32_RR2_MUL_32:
+        gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MUL_64:
+        gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+                     cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MULS_32:
+        gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+                            cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MUL_U_64:
+        gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+                     cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MULS_U_32:
+        gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
+                            cpu_gpr_d[r2]);
+        break;
+    }
+}
+
 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
 {
     int op1;
@@ -5218,6 +5251,10 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
     case OPCM_32_RR1_MULQ:
         decode_rr1_mulq(env, ctx);
         break;
+/* RR2 format */
+    case OPCM_32_RR2_MUL:
+        decode_rr2_mul(env, ctx);
+        break;
     }
 }
 
-- 
2.2.2

  parent reply	other threads:[~2015-01-27 11:08 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-27 12:09 [Qemu-devel] [PULL v2 0/9] tricore patches Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 1/9] target-tricore: Add missing ULL suffix on 64 bit constant Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 2/9] target-tricore: Several translator and cpu model fixes Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 3/9] target-tricore: calculate av bits before saturation Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 4/9] target-tricore: Fix bugs found by coverity Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 5/9] target-tricore: split up suov32 into suov32_pos and suov32_neg Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 6/9] target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode Bastian Koppelmann
2015-01-27 12:09 ` Bastian Koppelmann [this message]
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 8/9] target-tricore: Add instructions of RRPW opcode format Bastian Koppelmann
2015-01-27 12:09 ` [Qemu-devel] [PULL v2 9/9] target-tricore: Add instructions of RRR " Bastian Koppelmann
2015-01-27 12:47 ` [Qemu-devel] [PULL v2 0/9] tricore patches Peter Maydell

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