From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGTxi-0007a0-VF for qemu-devel@nongnu.org; Wed, 28 Jan 2015 09:51:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YGTxd-0005dG-T4 for qemu-devel@nongnu.org; Wed, 28 Jan 2015 09:51:22 -0500 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:37734) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGTxd-0005d1-Lc for qemu-devel@nongnu.org; Wed, 28 Jan 2015 09:51:17 -0500 Received: by mail-pa0-f42.google.com with SMTP id bj1so26112529pad.1 for ; Wed, 28 Jan 2015 06:51:17 -0800 (PST) From: Xiangyu Hu Date: Wed, 28 Jan 2015 14:51:06 +0000 Message-Id: <1422456666-12270-1-git-send-email-libhu.so@gmail.com> Subject: [Qemu-devel] [PATCH] FMULX should flushes operators to zero when FZ is set. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Xiangyu Hu The difference between FMULX and FMUL is that FMULX will return 2.0f when one operator is FPInfinity and the other one is FPZero, whilst FMUL will return a Default NaN. Without this patch, the emulation would result in inconsistency. Signed-off-by: Xiangyu Hu --- target-arm/helper-a64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 81066ca..ebd9247 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -135,6 +135,9 @@ float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp) { float_status *fpst = fpstp; + a = float32_squash_input_denormal(a, fpst); + b = float32_squash_input_denormal(b, fpst); + if ((float32_is_zero(a) && float32_is_infinity(b)) || (float32_is_infinity(a) && float32_is_zero(b))) { /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ @@ -148,6 +151,9 @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp) { float_status *fpst = fpstp; + a = float64_squash_input_denormal(a, fpst); + b = float64_squash_input_denormal(b, fpst); + if ((float64_is_zero(a) && float64_is_infinity(b)) || (float64_is_infinity(a) && float64_is_zero(b))) { /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ -- 1.9.1