From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YHphG-00072q-TW for qemu-devel@nongnu.org; Sun, 01 Feb 2015 03:16:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YHph9-0006RV-EI for qemu-devel@nongnu.org; Sun, 01 Feb 2015 03:15:58 -0500 Received: from smtp2-g21.free.fr ([2a01:e0c:1:1599::11]:18277) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YHph9-0006RE-5o for qemu-devel@nongnu.org; Sun, 01 Feb 2015 03:15:51 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Sun, 1 Feb 2015 09:12:55 +0100 Message-Id: <1422778376-32141-7-git-send-email-hpoussin@reactos.org> In-Reply-To: <1422778376-32141-1-git-send-email-hpoussin@reactos.org> References: <1422778376-32141-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 6/7] gt64xxx: remove isa_mem_base usage List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Leon Alrae , Aurelien Jarno Create a custom address space for PCI memory region and use it for the PC= I bus. Dynamically handle PCI0 Mem0 and PCI0 Mem1 regions, as already done for P= CI0 IO. Signed-off-by: Herv=C3=A9 Poussineau --- hw/mips/gt64xxx_pci.c | 95 +++++++++++++++++++++++++++++++++++--------= ------ 1 file changed, 68 insertions(+), 27 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 1f2fe5f..10fcca3 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -239,7 +239,11 @@ typedef struct GT64120State { =20 uint32_t regs[GT_REGS]; PCI_MAPPING_ENTRY(PCI0IO); + PCI_MAPPING_ENTRY(PCI0M0); + PCI_MAPPING_ENTRY(PCI0M1); PCI_MAPPING_ENTRY(ISD); + MemoryRegion pci0_mem; + AddressSpace pci0_mem_as; } GT64120State; =20 /* Adjust range to avoid touching space which isn't mappable via PCI */ @@ -290,25 +294,63 @@ static void gt64120_isd_mapping(GT64120State *s) =20 static void gt64120_pci_mapping(GT64120State *s) { - /* Update IO mapping */ - if ((s->regs[GT_PCI0IOLD] & 0x7f) <=3D s->regs[GT_PCI0IOHD]) - { - /* Unmap old IO address */ - if (s->PCI0IO_length) - { - memory_region_del_subregion(get_system_memory(), &s->PCI0IO_me= m); - object_unparent(OBJECT(&s->PCI0IO_mem)); - } - /* Map new IO address */ - s->PCI0IO_start =3D s->regs[GT_PCI0IOLD] << 21; - s->PCI0IO_length =3D ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI= 0IOLD] & 0x7f)) << 21; - isa_mem_base =3D s->PCI0IO_start; - if (s->PCI0IO_length) { - memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio"= , - get_system_io(), 0, s->PCI0IO_length)= ; - memory_region_add_subregion(get_system_memory(), s->PCI0IO_sta= rt, - &s->PCI0IO_mem); - } + /* Update PCI0IO mapping */ + if ((s->regs[GT_PCI0IOLD] & 0x7f) <=3D s->regs[GT_PCI0IOHD]) { + /* Unmap old IO address */ + if (s->PCI0IO_length) { + memory_region_del_subregion(get_system_memory(), &s->PCI0IO_= mem); + object_unparent(OBJECT(&s->PCI0IO_mem)); + } + /* Map new IO address */ + s->PCI0IO_start =3D s->regs[GT_PCI0IOLD] << 21; + s->PCI0IO_length =3D ((s->regs[GT_PCI0IOHD] + 1) - + (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; + if (s->PCI0IO_length) { + memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io= ", + get_system_io(), 0, s->PCI0IO_lengt= h); + memory_region_add_subregion(get_system_memory(), s->PCI0IO_s= tart, + &s->PCI0IO_mem); + } + } + + /* Update PCI0M0 mapping */ + if ((s->regs[GT_PCI0M0LD] & 0x7f) <=3D s->regs[GT_PCI0M0HD]) { + /* Unmap old MEM address */ + if (s->PCI0M0_length) { + memory_region_del_subregion(get_system_memory(), &s->PCI0M0_= mem); + object_unparent(OBJECT(&s->PCI0M0_mem)); + } + /* Map new mem address */ + s->PCI0M0_start =3D s->regs[GT_PCI0M0LD] << 21; + s->PCI0M0_length =3D ((s->regs[GT_PCI0M0HD] + 1) - + (s->regs[GT_PCI0M0LD] & 0x7f)) << 21; + if (s->PCI0M0_length) { + memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-me= m0", + &s->pci0_mem, s->PCI0M0_start, + s->PCI0M0_length); + memory_region_add_subregion(get_system_memory(), s->PCI0M0_s= tart, + &s->PCI0M0_mem); + } + } + + /* Update PCI0M1 mapping */ + if ((s->regs[GT_PCI0M1LD] & 0x7f) <=3D s->regs[GT_PCI0M1HD]) { + /* Unmap old MEM address */ + if (s->PCI0M1_length) { + memory_region_del_subregion(get_system_memory(), &s->PCI0M1_= mem); + object_unparent(OBJECT(&s->PCI0M1_mem)); + } + /* Map new mem address */ + s->PCI0M1_start =3D s->regs[GT_PCI0M1LD] << 21; + s->PCI0M1_length =3D ((s->regs[GT_PCI0M1HD] + 1) - + (s->regs[GT_PCI0M1LD] & 0x7f)) << 21; + if (s->PCI0M1_length) { + memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-me= m1", + &s->pci0_mem, s->PCI0M1_start, + s->PCI0M1_length); + memory_region_add_subregion(get_system_memory(), s->PCI0M1_s= tart, + &s->PCI0M1_mem); + } } } =20 @@ -363,10 +405,12 @@ static void gt64120_writel (void *opaque, hwaddr ad= dr, case GT_PCI0M0LD: s->regs[GT_PCI0M0LD] =3D val & 0x00007fff; s->regs[GT_PCI0M0REMAP] =3D val & 0x000007ff; + gt64120_pci_mapping(s); break; case GT_PCI0M1LD: s->regs[GT_PCI0M1LD] =3D val & 0x00007fff; s->regs[GT_PCI0M1REMAP] =3D val & 0x000007ff; + gt64120_pci_mapping(s); break; case GT_PCI1IOLD: s->regs[GT_PCI1IOLD] =3D val & 0x00007fff; @@ -380,12 +424,12 @@ static void gt64120_writel (void *opaque, hwaddr ad= dr, s->regs[GT_PCI1M1LD] =3D val & 0x00007fff; s->regs[GT_PCI1M1REMAP] =3D val & 0x000007ff; break; + case GT_PCI0M0HD: + case GT_PCI0M1HD: case GT_PCI0IOHD: s->regs[saddr] =3D val & 0x0000007f; gt64120_pci_mapping(s); break; - case GT_PCI0M0HD: - case GT_PCI0M1HD: case GT_PCI1IOHD: case GT_PCI1M0HD: case GT_PCI1M1HD: @@ -1124,10 +1168,12 @@ PCIBus *gt64120_register(qemu_irq *pic) qdev_init_nofail(dev); d =3D GT64120_PCI_HOST_BRIDGE(dev); phb =3D PCI_HOST_BRIDGE(dev); + memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX= ); + address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); phb->bus =3D pci_register_bus(dev, "pci", gt64120_pci_set_irq, gt64120_pci_map_irq= , pic, - get_system_memory(), + &d->pci0_mem, get_system_io(), PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "is= d-mem", 0x1000); @@ -1142,11 +1188,6 @@ static int gt64120_init(SysBusDevice *dev) =20 s =3D GT64120_PCI_HOST_BRIDGE(dev); =20 - /* FIXME: This value is computed from registers during reset, but so= me - devices (e.g. VGA card) need to know it when they are registered. - This also mean that changing the register to change the mapping - does not fully work. */ - isa_mem_base =3D 0x10000000; qemu_register_reset(gt64120_reset, s); return 0; } --=20 1.7.10.4