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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS
Date: Thu,  5 Feb 2015 14:02:49 +0000	[thread overview]
Message-ID: <1423144987-11425-11-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org>

The helper functions for FRECPS and FRSQRTS have special case
handling that includes checks for zero inputs, so squash input
denormals if necessary before those checks. This fixes incorrect
output when the FPCR DZ bit is set to enable squashing of input
denormals.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
---
 target-arm/helper-a64.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index ebd9247..8aa40e9 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -229,6 +229,9 @@ float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
+    a = float32_squash_input_denormal(a, fpst);
+    b = float32_squash_input_denormal(b, fpst);
+
     a = float32_chs(a);
     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
         (float32_is_infinity(b) && float32_is_zero(a))) {
@@ -241,6 +244,9 @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
+    a = float64_squash_input_denormal(a, fpst);
+    b = float64_squash_input_denormal(b, fpst);
+
     a = float64_chs(a);
     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
         (float64_is_infinity(b) && float64_is_zero(a))) {
@@ -253,6 +259,9 @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
+    a = float32_squash_input_denormal(a, fpst);
+    b = float32_squash_input_denormal(b, fpst);
+
     a = float32_chs(a);
     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
         (float32_is_infinity(b) && float32_is_zero(a))) {
@@ -265,6 +274,9 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
+    a = float64_squash_input_denormal(a, fpst);
+    b = float64_squash_input_denormal(b, fpst);
+
     a = float64_chs(a);
     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
         (float64_is_infinity(b) && float64_is_zero(a))) {
-- 
1.9.1

  parent reply	other threads:[~2015-02-05 14:03 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-05 14:02 [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 01/28] target_arm: Remove memory region init from armv7m_init Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 02/28] target_arm: Parameterise the irq lines for armv7m_init Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 05/28] target-arm: Change reset to highest available EL Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 07/28] target-arm: Split NO_MIGRATE into ALIAS and NO_RAW Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses are handled Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set Peter Maydell
2015-02-05 14:02 ` Peter Maydell [this message]
2015-02-05 14:02 ` [Qemu-devel] [PULL 11/28] target-arm: check that LSB <= MSB in BFI instruction Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 12/28] hw/arm/virt: explain device-to-transport mapping in create_virtio_devices() Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7 Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 17/28] target-arm: Use correct mmu_idx for unprivileged loads and stores Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write() Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 20/28] target-arm: Pass mmu_idx to get_phys_addr() Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr() Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 22/28] target-arm: Reindent ancient page-table-walk code Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 23/28] target-arm: Fix brace style in reindented code Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 24/28] disas/libvixl: Update to upstream VIXL 1.7 Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 25/28] disas/arm-a64.cc: Tell libvixl correct code addresses Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 26/28] target-arm: KVM64: Get and Sync up guest register state like kvm32 Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 27/28] target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64 Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 28/28] target-arm: fix for exponent comparison in recpe_f64 Peter Maydell
2015-02-05 15:21 ` [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell

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