From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49932) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJN1i-0001VN-72 for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YJN1d-0007Wc-Ll for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:26 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54955) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJN1d-0007RD-GL for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:21 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YJN1Q-0002zm-16 for qemu-devel@nongnu.org; Thu, 05 Feb 2015 14:03:08 +0000 From: Peter Maydell Date: Thu, 5 Feb 2015 14:02:52 +0000 Message-Id: <1423144987-11425-14-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org> References: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Support guest CPUs which need 7 MMU index values. Add a comment about what would be required to raise the limit further (trivial for 8, TCG backend rework for 9 or more). Signed-off-by: Peter Maydell Reviewed-by: Greg Bellows Reviewed-by: Richard Henderson --- include/exec/cpu_ldst.h | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 0e825ea..1673287 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -244,9 +244,31 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); #undef MEMSUFFIX #endif /* (NB_MMU_MODES >= 6) */ -#if (NB_MMU_MODES > 6) -#error "NB_MMU_MODES > 6 is not supported for now" -#endif /* (NB_MMU_MODES > 6) */ +#if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX) + +#define CPU_MMU_INDEX 6 +#define MEMSUFFIX MMU_MODE6_SUFFIX +#define DATA_SIZE 1 +#include "exec/cpu_ldst_template.h" + +#define DATA_SIZE 2 +#include "exec/cpu_ldst_template.h" + +#define DATA_SIZE 4 +#include "exec/cpu_ldst_template.h" + +#define DATA_SIZE 8 +#include "exec/cpu_ldst_template.h" +#undef CPU_MMU_INDEX +#undef MEMSUFFIX +#endif /* (NB_MMU_MODES >= 7) */ + +#if (NB_MMU_MODES > 7) +/* Note that supporting NB_MMU_MODES == 9 would require + * changes to at least the ARM TCG backend. + */ +#error "NB_MMU_MODES > 7 is not supported for now" +#endif /* (NB_MMU_MODES > 7) */ /* these access are slower, they must be as rare as possible */ #define CPU_MMU_INDEX (cpu_mmu_index(env)) -- 1.9.1