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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 25/28] disas/arm-a64.cc: Tell libvixl correct code addresses
Date: Thu,  5 Feb 2015 14:03:04 +0000	[thread overview]
Message-ID: <1423144987-11425-26-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org>

disassembling relative branches in code which doesn't reside at
what the guest CPU would think its execution address is. Use
the new MapCodeAddress() API to tell libvixl where the code is
from the guest CPU's point of view so it can get the target
addresses right.

Previous disassembly:

0x0000000040000000:  580000c0      ldr x0, pc+24 (addr 0x7f6cb7020434)
0x0000000040000004:  aa1f03e1      mov x1, xzr
0x0000000040000008:  aa1f03e2      mov x2, xzr
0x000000004000000c:  aa1f03e3      mov x3, xzr
0x0000000040000010:  58000084      ldr x4, pc+16 (addr 0x7f6cb702042c)
0x0000000040000014:  d61f0080      br x4

Fixed disassembly:
0x0000000040000000:  580000c0      ldr x0, pc+24 (addr 0x40000018)
0x0000000040000004:  aa1f03e1      mov x1, xzr
0x0000000040000008:  aa1f03e2      mov x2, xzr
0x000000004000000c:  aa1f03e3      mov x3, xzr
0x0000000040000010:  58000084      ldr x4, pc+16 (addr 0x40000020)
0x0000000040000014:  d61f0080      br x4

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1422274779-13359-3-git-send-email-peter.maydell@linaro.org
---
 disas/arm-a64.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/disas/arm-a64.cc b/disas/arm-a64.cc
index ca29f6f..e04f946 100644
--- a/disas/arm-a64.cc
+++ b/disas/arm-a64.cc
@@ -67,7 +67,8 @@ static void vixl_init(FILE *f) {
 int print_insn_arm_a64(uint64_t addr, disassemble_info *info)
 {
     uint8_t bytes[INSN_SIZE];
-    uint32_t instr;
+    uint32_t instrval;
+    const Instruction *instr;
     int status;
 
     status = info->read_memory_func(addr, bytes, INSN_SIZE, info);
@@ -80,8 +81,10 @@ int print_insn_arm_a64(uint64_t addr, disassemble_info *info)
         vixl_init(info->stream);
     }
 
-    instr = bytes[0] | bytes[1] << 8 | bytes[2] << 16 | bytes[3] << 24;
-    vixl_decoder->Decode(reinterpret_cast<Instruction*>(&instr));
+    instrval = bytes[0] | bytes[1] << 8 | bytes[2] << 16 | bytes[3] << 24;
+    instr = reinterpret_cast<const Instruction *>(&instrval);
+    vixl_disasm->MapCodeAddress(addr, instr);
+    vixl_decoder->Decode(instr);
 
     return INSN_SIZE;
 }
-- 
1.9.1

  parent reply	other threads:[~2015-02-05 14:03 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-05 14:02 [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 01/28] target_arm: Remove memory region init from armv7m_init Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 02/28] target_arm: Parameterise the irq lines for armv7m_init Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 05/28] target-arm: Change reset to highest available EL Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 07/28] target-arm: Split NO_MIGRATE into ALIAS and NO_RAW Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses are handled Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 11/28] target-arm: check that LSB <= MSB in BFI instruction Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 12/28] hw/arm/virt: explain device-to-transport mapping in create_virtio_devices() Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7 Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 17/28] target-arm: Use correct mmu_idx for unprivileged loads and stores Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write() Peter Maydell
2015-02-05 14:02 ` [Qemu-devel] [PULL 20/28] target-arm: Pass mmu_idx to get_phys_addr() Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr() Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 22/28] target-arm: Reindent ancient page-table-walk code Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 23/28] target-arm: Fix brace style in reindented code Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 24/28] disas/libvixl: Update to upstream VIXL 1.7 Peter Maydell
2015-02-05 14:03 ` Peter Maydell [this message]
2015-02-05 14:03 ` [Qemu-devel] [PULL 26/28] target-arm: KVM64: Get and Sync up guest register state like kvm32 Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 27/28] target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64 Peter Maydell
2015-02-05 14:03 ` [Qemu-devel] [PULL 28/28] target-arm: fix for exponent comparison in recpe_f64 Peter Maydell
2015-02-05 15:21 ` [Qemu-devel] [PULL 00/28] target-arm queue Peter Maydell

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