From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJN1h-0001Uv-Ii for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YJN1g-0007YQ-Bp for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:25 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54955) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJN1g-0007RD-3k for qemu-devel@nongnu.org; Thu, 05 Feb 2015 09:03:24 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1YJN1P-0002zD-KC for qemu-devel@nongnu.org; Thu, 05 Feb 2015 14:03:07 +0000 From: Peter Maydell Date: Thu, 5 Feb 2015 14:02:45 +0000 Message-Id: <1423144987-11425-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org> References: <1423144987-11425-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Greg Bellows Added CP register definitions for SP_EL1 and SP_EL2. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1422029835-4696-5-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 29f3b62..79c54a9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_RW, .accessfn = sp_el0_access, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, + { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL2_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_MIGRATE, @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), .resetvalue = 0 }, + { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_NO_MIGRATE, + .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, REGINFO_SENTINEL }; -- 1.9.1