From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJQQu-0000CN-1t for qemu-devel@nongnu.org; Thu, 05 Feb 2015 12:41:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YJQQs-0004n9-NZ for qemu-devel@nongnu.org; Thu, 05 Feb 2015 12:41:40 -0500 Received: from mx1.redhat.com ([209.132.183.28]:44990) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJQQs-0004mv-H9 for qemu-devel@nongnu.org; Thu, 05 Feb 2015 12:41:38 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t15Hfb47003904 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Thu, 5 Feb 2015 12:41:38 -0500 From: John Snow Date: Thu, 5 Feb 2015 12:41:16 -0500 Message-Id: <1423158090-25580-6-git-send-email-jsnow@redhat.com> In-Reply-To: <1423158090-25580-1-git-send-email-jsnow@redhat.com> References: <1423158090-25580-1-git-send-email-jsnow@redhat.com> Subject: [Qemu-devel] [PATCH v3 05/19] libqos/ahci: Add ahci_port_check_error helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: famz@redhat.com, mst@redhat.com, armbru@redhat.com, stefanha@redhat.com, pbonzini@redhat.com, John Snow ahci_port_check_error checks a given port's error registers and asserts that everything from the port-level view is still OK. Signed-off-by: John Snow Reviewed-by: Paolo Bonzini --- tests/ahci-test.c | 8 +------- tests/libqos/ahci.c | 22 ++++++++++++++++++++++ tests/libqos/ahci.h | 1 + 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/tests/ahci-test.c b/tests/ahci-test.c index fbf329e..a3e8f12 100644 --- a/tests/ahci-test.c +++ b/tests/ahci-test.c @@ -747,6 +747,7 @@ static void ahci_test_identify(AHCIQState *ahci) while (BITSET(ahci_px_rreg(ahci, i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) { usleep(50); } + ahci_port_check_error(ahci, i); /* Check for expected interrupts */ reg = ahci_px_rreg(ahci, i, AHCI_PX_IS); @@ -760,13 +761,6 @@ static void ahci_test_identify(AHCIQState *ahci) AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS); g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_IS), ==, 0); - /* Check for errors. */ - reg = ahci_px_rreg(ahci, i, AHCI_PX_SERR); - g_assert_cmphex(reg, ==, 0); - reg = ahci_px_rreg(ahci, i, AHCI_PX_TFD); - ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR); - ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); - /* Investigate the CMD, assert that we read 512 bytes */ ahci_get_command_header(ahci, i, cx, &cmd); g_assert_cmphex(512, ==, cmd.prdbc); diff --git a/tests/libqos/ahci.c b/tests/libqos/ahci.c index 9179711..f3fa472 100644 --- a/tests/libqos/ahci.c +++ b/tests/libqos/ahci.c @@ -311,6 +311,28 @@ void ahci_port_clear(AHCIQState *ahci, uint8_t port) qmemset(ahci->port[port].fb, 0x00, 0x100); } +/** + * Check a port for errors. + */ +void ahci_port_check_error(AHCIQState *ahci, uint8_t port) +{ + uint32_t reg; + + /* The upper 9 bits of the IS register all indicate errors. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + reg >>= 23; + g_assert_cmphex(reg, ==, 0); + + /* The Sata Error Register should be empty. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); + g_assert_cmphex(reg, ==, 0); + + /* The TFD also has two error sections. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); + ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR); + ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); +} + /* Get the command in #slot of port #port. */ void ahci_get_command_header(AHCIQState *ahci, uint8_t port, uint8_t slot, AHCICommandHeader *cmd) diff --git a/tests/libqos/ahci.h b/tests/libqos/ahci.h index 0835be4..af62a8a 100644 --- a/tests/libqos/ahci.h +++ b/tests/libqos/ahci.h @@ -433,6 +433,7 @@ void start_ahci_device(AHCIQState *ahci); void ahci_hba_enable(AHCIQState *ahci); unsigned ahci_port_select(AHCIQState *ahci); void ahci_port_clear(AHCIQState *ahci, uint8_t port); +void ahci_port_check_error(AHCIQState *ahci, uint8_t port); void ahci_get_command_header(AHCIQState *ahci, uint8_t port, uint8_t slot, AHCICommandHeader *cmd); void ahci_set_command_header(AHCIQState *ahci, uint8_t port, -- 1.9.3