From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40319) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJjzC-0003TV-Rh for qemu-devel@nongnu.org; Fri, 06 Feb 2015 09:34:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YJjz8-00044B-TC for qemu-devel@nongnu.org; Fri, 06 Feb 2015 09:34:22 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54960) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YJjz8-00043L-Ms for qemu-devel@nongnu.org; Fri, 06 Feb 2015 09:34:18 -0500 From: Peter Maydell Date: Fri, 6 Feb 2015 14:34:07 +0000 Message-Id: <1423233250-15853-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1423233250-15853-1-git-send-email-peter.maydell@linaro.org> References: <1423233250-15853-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 1/4] target-arm: A64: Fix shifts into sign bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Richard Henderson , patches@linaro.org Fix attempts to shift into the sign bit of an int, which is undefined behaviour in C and warned about by the clang sanitizer. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index acf4b16..d3801c5 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1077,7 +1077,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; - if (insn & (1 << 31)) { + if (insn & (1U << 31)) { /* C5.6.26 BL Branch with link */ tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); } @@ -1271,7 +1271,7 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) TCGv_i32 nzcv = tcg_temp_new_i32(); /* build bit 31, N */ - tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31)); + tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); /* build bit 30, Z */ tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); @@ -1296,7 +1296,7 @@ static void gen_set_nzcv(TCGv_i64 tcg_rt) tcg_gen_trunc_i64_i32(nzcv, tcg_rt); /* bit 31, N */ - tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31)); + tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); /* bit 30, Z */ tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); -- 1.9.1