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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net
Subject: [Qemu-devel] [PATCH v2 0/6] TriCore: Add RRR1 and RRR2 instructions
Date: Wed, 11 Feb 2015 16:48:57 +0000	[thread overview]
Message-ID: <1423673343-25688-1-git-send-email-kbastian@mail.uni-paderborn.de> (raw)

Hi,

the patchset fixes two minor bugs and takes care of all the packed/fixed point
mac instructions. So far I only implemented all the multiply-add instructions,
since the multiply-sub instructions are similar and I don't want the reviewers
to find the same mistakes twice. Once these are reviewed I will send another
patchset containing all the multiply-sub instructions.
I do plan on mirroring the multiply-add instructions, which seems okay. However
if there are ideas to make this more clean, let me know.

Cheers,
Bastian

v1 -> v2:
    * fix obvious style issues found by checkpatch

Bastian Koppelmann (6):
  target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper
  target-tricore: fix msub32_suov return wrong results
  target-tricore: Add instructions of RRR2 opcode format
  target-tricore: Add instructions of RRR1 opcode format, which have
    0x83 as first opcode
  target-tricore: Add instructions of RRR1 opcode format, which have
    0x43 as first opcode
  target-tricore: Add instructions of RRR1 opcode format, which have
    0xc3 as first opcode

 target-tricore/helper.h          |    9 +
 target-tricore/op_helper.c       |  374 +++++++++-
 target-tricore/translate.c       | 1391 ++++++++++++++++++++++++++++++++++++--
 target-tricore/tricore-opcodes.h |   10 +-
 4 files changed, 1728 insertions(+), 56 deletions(-)

--
2.3.0

             reply	other threads:[~2015-02-11 15:47 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-11 16:48 Bastian Koppelmann [this message]
2015-02-11 16:48 ` [Qemu-devel] [PATCH v2 1/6] target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper Bastian Koppelmann
2015-02-11 16:48 ` [Qemu-devel] [PATCH v2 2/6] target-tricore: fix msub32_suov return wrong results Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 3/6] target-tricore: Add instructions of RRR2 opcode format Bastian Koppelmann
2015-02-17 19:56   ` Richard Henderson
2015-02-18  0:06     ` Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 4/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 5/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x43 " Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 6/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 " Bastian Koppelmann
2015-02-17 13:17 ` [Qemu-devel] [PATCH v2 0/6] TriCore: Add RRR1 and RRR2 instructions Bastian Koppelmann
2015-02-17 20:12 ` Richard Henderson

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