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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net
Subject: [Qemu-devel] [PATCH v2 2/6] target-tricore: fix msub32_suov return wrong results
Date: Wed, 11 Feb 2015 16:48:59 +0000	[thread overview]
Message-ID: <1423673343-25688-3-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1423673343-25688-1-git-send-email-kbastian@mail.uni-paderborn.de>

If the signed result of the multiplication overflows, we would get a negative
value, which would result in a addition instead of a subtraction.

Now we do the overflow calculation and saturation by hand instead of using
suov32_neg.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/op_helper.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index ed26b30..08bf4ae 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -443,13 +443,28 @@ target_ulong helper_msub32_ssov(CPUTriCoreState *env, target_ulong r1,
 target_ulong helper_msub32_suov(CPUTriCoreState *env, target_ulong r1,
                                 target_ulong r2, target_ulong r3)
 {
-    int64_t t1 = extract64(r1, 0, 32);
-    int64_t t2 = extract64(r2, 0, 32);
-    int64_t t3 = extract64(r3, 0, 32);
-    int64_t result;
+    uint64_t t1 = extract64(r1, 0, 32);
+    uint64_t t2 = extract64(r2, 0, 32);
+    uint64_t t3 = extract64(r3, 0, 32);
+    uint64_t result;
+    uint64_t mul;
 
-    result = t2 - (t1 * t3);
-    return suov32_neg(env, result);
+    mul = (t1 * t3);
+    result = t2 - mul;
+
+    env->PSW_USB_AV = result ^ result * 2u;
+    env->PSW_USB_SAV |= env->PSW_USB_AV;
+    /* we calculate ovf by hand here, because the multiplication can overflow on
+       the host, which would give false results if we compare to less than
+       zero */
+    if (mul > t2) {
+        env->PSW_USB_V = (1 << 31);
+        env->PSW_USB_SV = (1 << 31);
+        result = 0;
+    } else {
+        env->PSW_USB_V = 0;
+    }
+    return result;
 }
 
 uint64_t helper_msub64_ssov(CPUTriCoreState *env, target_ulong r1,
-- 
2.3.0

  parent reply	other threads:[~2015-02-11 15:47 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-11 16:48 [Qemu-devel] [PATCH v2 0/6] TriCore: Add RRR1 and RRR2 instructions Bastian Koppelmann
2015-02-11 16:48 ` [Qemu-devel] [PATCH v2 1/6] target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper Bastian Koppelmann
2015-02-11 16:48 ` Bastian Koppelmann [this message]
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 3/6] target-tricore: Add instructions of RRR2 opcode format Bastian Koppelmann
2015-02-17 19:56   ` Richard Henderson
2015-02-18  0:06     ` Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 4/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as first opcode Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 5/6] target-tricore: Add instructions of RRR1 opcode format, which have 0x43 " Bastian Koppelmann
2015-02-11 16:49 ` [Qemu-devel] [PATCH v2 6/6] target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 " Bastian Koppelmann
2015-02-17 13:17 ` [Qemu-devel] [PATCH v2 0/6] TriCore: Add RRR1 and RRR2 instructions Bastian Koppelmann
2015-02-17 20:12 ` Richard Henderson

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