From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YMHgR-0006tt-M8 for qemu-devel@nongnu.org; Fri, 13 Feb 2015 09:57:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YMHgG-0000TI-Ji for qemu-devel@nongnu.org; Fri, 13 Feb 2015 09:57:31 -0500 Received: from mail-we0-x236.google.com ([2a00:1450:400c:c03::236]:44219) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YMHgG-0000TA-D4 for qemu-devel@nongnu.org; Fri, 13 Feb 2015 09:57:20 -0500 Received: by mail-we0-f182.google.com with SMTP id m14so11201560wev.13 for ; Fri, 13 Feb 2015 06:57:19 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 13 Feb 2015 15:57:09 +0100 Message-Id: <1423839431-3563-2-git-send-email-pbonzini@redhat.com> In-Reply-To: <1423839431-3563-1-git-send-email-pbonzini@redhat.com> References: <1423839431-3563-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 1/3] pcie: remove mmconfig memory leak and wrap mmconfig update with transaction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: mjrosato@linux.vnet.ibm.com, alex.williamson@redhat.com, mst@redhat.com This memory leak was introduced inadvertently by omitting object_unparent. A better fix is to use the new memory_region_set_size instead of destroying and recreating the MMIO region on the fly. Also, ensure that unmapping and remapping the region is done atomically. Signed-off-by: Paolo Bonzini --- hw/pci/pcie_host.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index dfb4a2b..d8afba8 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -88,6 +88,8 @@ static void pcie_host_init(Object *obj) PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); e->base_addr = PCIE_BASE_ADDR_UNMAPPED; + memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e, "pcie-mmcfg-mmio", + PCIE_MMCFG_SIZE_MAX); } void pcie_host_mmcfg_unmap(PCIExpressHost *e) @@ -104,8 +106,7 @@ void pcie_host_mmcfg_init(PCIExpressHost *e, uint32_t size) assert(size >= PCIE_MMCFG_SIZE_MIN); assert(size <= PCIE_MMCFG_SIZE_MAX); e->size = size; - memory_region_init_io(&e->mmio, OBJECT(e), &pcie_mmcfg_ops, e, - "pcie-mmcfg", e->size); + memory_region_set_size(&e->mmio, e->size); } void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr, @@ -121,10 +122,12 @@ void pcie_host_mmcfg_update(PCIExpressHost *e, hwaddr addr, uint32_t size) { + memory_region_transaction_begin(); pcie_host_mmcfg_unmap(e); if (enable) { pcie_host_mmcfg_map(e, addr, size); } + memory_region_transaction_commit(); } static const TypeInfo pcie_host_type_info = { -- 1.8.3.1