From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41833) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YNIvE-0005WR-Mf for qemu-devel@nongnu.org; Mon, 16 Feb 2015 05:29:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YNIvD-0006sl-R7 for qemu-devel@nongnu.org; Mon, 16 Feb 2015 05:29:00 -0500 From: Marcel Apfelbaum Date: Mon, 16 Feb 2015 11:54:14 +0200 Message-Id: <1424080457-13752-15-git-send-email-marcel@redhat.com> In-Reply-To: <1424080457-13752-1-git-send-email-marcel@redhat.com> References: <1424080457-13752-1-git-send-email-marcel@redhat.com> Subject: [Qemu-devel] [PATCH RFC V2 14/17] hw/pci: piix - suport multiple host bridges List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: seabios@seabios.org, kraxel@redhat.com, mst@redhat.com, quintela@redhat.com, agraf@suse.de, marcel@redhat.com, alex.williamson@redhat.com, kevin@koconnor.net, qemu-ppc@nongnu.org, hare@suse.de, imammedo@redhat.com, amit.shah@redhat.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net From: Marcel Apfelbaum Instead of assuming it has only one bus, it enumerates all the host bridges until it finds the one with bus number corresponding with the config register. Signed-off-by: Marcel Apfelbaum --- hw/pci-host/piix.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 970b9e9..7310b4c 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -255,6 +255,61 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, visit_type_uint64(v, &w64.end, name, errp); } +static PCIBus *i440fx_find_primary_bus(int bus_num) +{ + PCIHostState *host; + PCIBus *bus = NULL; + int current = -1; + + HOST_BRIDGE_FOREACH(host) { + int b = pci_bus_num(host->bus); + if (b <= bus_num && b > current) { + current = b; + bus = host->bus; + } + } + + return bus; +} + +static void i440fx_pcihost_data_write(void *opaque, hwaddr addr, + uint64_t val, unsigned len) +{ + uint32_t config_reg = PCI_HOST_BRIDGE(opaque)->config_reg; + + if (config_reg & (1u << 31)) { + int bus_num = (config_reg >> 16) & 0xFF; + PCIBus *bus = i440fx_find_primary_bus(bus_num); + + if (bus) { + pci_data_write(bus, config_reg | (addr & 3), val, len); + } + } +} + +static uint64_t i440fx_pcihost_data_read(void *opaque, + hwaddr addr, unsigned len) +{ + uint32_t config_reg = PCI_HOST_BRIDGE(opaque)->config_reg; + + if (config_reg & (1U << 31)) { + int bus_num = (config_reg >> 16) & 0xFF; + PCIBus *bus = i440fx_find_primary_bus(bus_num); + + if (bus) { + return pci_data_read(bus, config_reg | (addr & 3), len); + } + } + + return 0xffffffff; +} + +const MemoryRegionOps i440fx_pcihost_data_le_ops = { + .read = i440fx_pcihost_data_read, + .write = i440fx_pcihost_data_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static void i440fx_pcihost_initfn(Object *obj) { PCIHostState *s = PCI_HOST_BRIDGE(obj); @@ -262,7 +317,7 @@ static void i440fx_pcihost_initfn(Object *obj) memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, "pci-conf-idx", 4); - memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, + memory_region_init_io(&s->data_mem, obj, &i440fx_pcihost_data_le_ops, s, "pci-conf-data", 4); object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", -- 2.1.0