qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Marcel Apfelbaum <marcel@redhat.com>
To: qemu-devel@nongnu.org
Cc: seabios@seabios.org, kraxel@redhat.com, mst@redhat.com,
	quintela@redhat.com, agraf@suse.de, marcel@redhat.com,
	alex.williamson@redhat.com, kevin@koconnor.net,
	qemu-ppc@nongnu.org, hare@suse.de, imammedo@redhat.com,
	amit.shah@redhat.com, pbonzini@redhat.com, leon.alrae@imgtec.com,
	aurelien@aurel32.net, rth@twiddle.net
Subject: [Qemu-devel] [PATCH RFC V2 05/17] hw/acpi: remove from root bus 0 the crs resources used by other busses.
Date: Mon, 16 Feb 2015 11:54:05 +0200	[thread overview]
Message-ID: <1424080457-13752-6-git-send-email-marcel@redhat.com> (raw)
In-Reply-To: <1424080457-13752-1-git-send-email-marcel@redhat.com>

If multiple root busses are used, root bus 0 cannot use all the
pci holes ranges. Remove the IO/mem ranges used by the other
primary busses.

Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
---
 hw/i386/acpi-build.c | 85 ++++++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 73 insertions(+), 12 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0822a20..b2b0036 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -870,6 +870,9 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
     int i;
     PciRangeQ io_ranges = QLIST_HEAD_INITIALIZER(io_ranges);
     PciRangeQ mem_ranges = QLIST_HEAD_INITIALIZER(mem_ranges);
+    PciMemoryRange range;
+    PciRangeEntry *entry;
+    int root_bus_limit = 0xFF;
 
     /* The current AML generator can cover the APIC ID range [0..255],
      * inclusive, for VCPU hotplug. */
@@ -897,6 +900,10 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
                 continue;
             }
 
+            if (bus_info->bus < root_bus_limit) {
+                root_bus_limit = bus_info->bus - 1;
+            }
+
             scope = acpi_scope("\\_SB");
             dev = acpi_device("PC%.02X", (uint8_t)bus_info->bus);
             aml_append(&dev, acpi_name_decl("_UID",
@@ -911,8 +918,6 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
             aml_append(&ssdt, scope);
         }
 
-        pci_range_list_free(&io_ranges);
-        pci_range_list_free(&mem_ranges);
         qapi_free_PciInfoList(info_list);
     }
 
@@ -921,26 +926,79 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
     crs = acpi_resource_template();
     aml_append(&crs,
         acpi_word_bus_number(acpi_min_fixed, acpi_max_fixed, acpi_pos_decode,
-                             0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
+                             0x0000, 0x0, root_bus_limit,
+                             0x0000, root_bus_limit + 1));
+
     aml_append(&crs, acpi_io(acpi_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
 
     aml_append(&crs,
         acpi_word_io(acpi_min_fixed, acpi_max_fixed,
                      acpi_pos_decode, acpi_entire_range,
                      0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
-    aml_append(&crs,
-        acpi_word_io(acpi_min_fixed, acpi_max_fixed,
-                     acpi_pos_decode, acpi_entire_range,
-                     0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
+
+    /* prepare PCI IO ranges */
+    range.base = 0x0D00;
+    range.limit = 0xFFFF;
+    if (QLIST_EMPTY(&io_ranges)) {
+        aml_append(&crs,
+            acpi_word_io(acpi_min_fixed, acpi_max_fixed,
+                         acpi_pos_decode, acpi_entire_range,
+                         0x0000, range.base, range.limit,
+                         0x0000, range.limit - range.base + 1));
+    } else {
+        QLIST_FOREACH(entry, &io_ranges, entry) {
+            if (range.base < entry->base) {
+                aml_append(&crs,
+                    acpi_word_io(acpi_min_fixed, acpi_max_fixed,
+                                 acpi_pos_decode, acpi_entire_range,
+                                 0x0000, range.base, entry->base - 1,
+                                 0x0000, entry->base - range.base));
+            }
+            range.base = entry->limit + 1;
+            if (!QLIST_NEXT(entry, entry)) {
+                aml_append(&crs,
+                    acpi_word_io(acpi_min_fixed, acpi_max_fixed,
+                                 acpi_pos_decode, acpi_entire_range,
+                                 0x0000, range.base, range.limit,
+                                 0x0000, range.limit - range.base + 1));
+            }
+        }
+    }
+
     aml_append(&crs,
         acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
                           acpi_cacheable, acpi_ReadWrite,
                           0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
-    aml_append(&crs,
-        acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
-                          acpi_non_cacheable, acpi_ReadWrite,
-                          0, pci->w32.begin, pci->w32.end - 1, 0,
-                          pci->w32.end - pci->w32.begin));
+
+    /* prepare PCI memory ranges */
+    range.base = pci->w32.begin;
+    range.limit = pci->w32.end - 1;
+    if (QLIST_EMPTY(&mem_ranges)) {
+        aml_append(&crs,
+            acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
+                              acpi_non_cacheable, acpi_ReadWrite,
+                              0, range.base, range.limit,
+                              0, range.limit - range.base + 1));
+    } else {
+        QLIST_FOREACH(entry, &mem_ranges, entry) {
+            if (range.base < entry->base) {
+                aml_append(&crs,
+                    acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
+                                      acpi_non_cacheable, acpi_ReadWrite,
+                                      0, range.base, entry->base - 1,
+                                      0, entry->base - range.base));
+            }
+            range.base = entry->limit + 1;
+            if (!QLIST_NEXT(entry, entry)) {
+                aml_append(&crs,
+                    acpi_dword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
+                                      acpi_non_cacheable, acpi_ReadWrite,
+                                      0, range.base, range.limit,
+                                      0, range.base - range.limit + 1));
+            }
+        }
+    }
+
     if (pci->w64.begin) {
         aml_append(&crs,
             acpi_qword_memory(acpi_pos_decode, acpi_min_fixed, acpi_max_fixed,
@@ -950,6 +1008,9 @@ build_ssdt(AcpiAml *table_aml, GArray *linker,
     }
     aml_append(&scope, acpi_name_decl("_CRS", crs));
 
+    pci_range_list_free(&io_ranges);
+    pci_range_list_free(&mem_ranges);
+
     /* reserve PCIHP resources */
     if (pm->pcihp_io_len) {
         dev = acpi_device("PHPR");
-- 
2.1.0

  parent reply	other threads:[~2015-02-16  9:56 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-16  9:54 [Qemu-devel] [PATCH RFC V2 00/17] hw/pc: implement multiple primary busses for pc machines Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 01/17] acpi: added needed acpi constructs Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 02/17] hw/acpi: add support for multiple root busses Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 03/17] hw/apci: add _PRT method for extra " Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 04/17] hw/acpi: add _CRS " Marcel Apfelbaum
2015-02-16 10:07   ` Igor Mammedov
2015-02-16 10:19     ` Marcel Apfelbaum
2015-02-16 11:37     ` Michael S. Tsirkin
2015-02-16 12:06   ` Marcel Apfelbaum
2015-02-16  9:54 ` Marcel Apfelbaum [this message]
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 06/17] hw/pci: move pci bus related code to separate files Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 07/17] hw/pci: made pci_bus_is_root a PCIBusClass method Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 08/17] hw/pci: made pci_bus_num " Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 09/17] hw/pci: introduce TYPE_PCI_MAIN_HOST_BRIDGE interface Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 10/17] hw/pci: removed 'rootbus nr is 0' assumption from qmp_pci_query Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 11/17] hw/pci: implement iteration over multiple host bridges Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 12/17] hw/pci: introduce PCI Expander Bridge (PXB) Marcel Apfelbaum
2015-02-16 12:58   ` Alexander Graf
2015-02-16 13:00     ` Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 13/17] hw/pci: inform bios if the system has more than one pci bridge Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 14/17] hw/pci: piix - suport multiple host bridges Marcel Apfelbaum
2015-02-16 13:00   ` Alexander Graf
2015-02-16 13:29     ` Marcel Apfelbaum
2015-02-20 14:33       ` Alexander Graf
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 15/17] hw/pxb: add map_irq func Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 16/17] hw/pci_bus: add support for NUMA nodes Marcel Apfelbaum
2015-02-16  9:54 ` [Qemu-devel] [PATCH RFC V2 17/17] hw/pxb: add numa_node parameter Marcel Apfelbaum

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1424080457-13752-6-git-send-email-marcel@redhat.com \
    --to=marcel@redhat.com \
    --cc=agraf@suse.de \
    --cc=alex.williamson@redhat.com \
    --cc=amit.shah@redhat.com \
    --cc=aurelien@aurel32.net \
    --cc=hare@suse.de \
    --cc=imammedo@redhat.com \
    --cc=kevin@koconnor.net \
    --cc=kraxel@redhat.com \
    --cc=leon.alrae@imgtec.com \
    --cc=mst@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=quintela@redhat.com \
    --cc=rth@twiddle.net \
    --cc=seabios@seabios.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).