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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 09/11] target-arm: Implement ccmp branchless
Date: Thu, 19 Feb 2015 13:14:27 -0800	[thread overview]
Message-ID: <1424380469-20138-10-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1424380469-20138-1-git-send-email-rth@twiddle.net>

This can allow much of a ccmp to be elided when particular
flags are subsequently dead.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/translate-a64.c | 62 ++++++++++++++++++++++++++++++----------------
 1 file changed, 41 insertions(+), 21 deletions(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 7549267..8171a1f 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3641,8 +3641,8 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
 static void disas_cc(DisasContext *s, uint32_t insn)
 {
     unsigned int sf, op, y, cond, rn, nzcv, is_imm;
-    TCGLabel *label_continue = NULL;
-    TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
+    TCGv_i64 tcg_t0, tcg_t1, tcg_t2, tcg_y, tcg_rn;
+    DisasCompare c;
 
     if (!extract32(insn, 29, 1)) {
         unallocated_encoding(s);
@@ -3660,19 +3660,13 @@ static void disas_cc(DisasContext *s, uint32_t insn)
     rn = extract32(insn, 5, 5);
     nzcv = extract32(insn, 0, 4);
 
-    if (cond < 0x0e) { /* not always */
-        TCGLabel *label_match = gen_new_label();
-        label_continue = gen_new_label();
-        arm_gen_test_cc(cond, label_match);
-        /* nomatch: */
-        tcg_tmp = tcg_temp_new_i64();
-        tcg_gen_movi_i64(tcg_tmp, nzcv << 28);
-        gen_set_nzcv(tcg_tmp);
-        tcg_temp_free_i64(tcg_tmp);
-        tcg_gen_br(label_continue);
-        gen_set_label(label_match);
-    }
-    /* match, or condition is always */
+    /* Set T0 = !COND.  */
+    tcg_t0 = tcg_temp_new_i64();
+    arm_test_cc(&c, cond);
+    tcg_gen_setcondi_i64(tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
+    arm_free_cc(&c);
+
+    /* Load the arguments for the new comparison.  */
     if (is_imm) {
         tcg_y = new_tmp_a64(s);
         tcg_gen_movi_i64(tcg_y, y);
@@ -3681,17 +3675,43 @@ static void disas_cc(DisasContext *s, uint32_t insn)
     }
     tcg_rn = cpu_reg(s, rn);
 
-    tcg_tmp = tcg_temp_new_i64();
+    /* Set the flags for the new comparison.  */
+    tcg_t1 = tcg_temp_new_i64();
     if (op) {
-        gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+        gen_sub_CC(sf, tcg_t1, tcg_rn, tcg_y);
     } else {
-        gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+        gen_add_CC(sf, tcg_t1, tcg_rn, tcg_y);
     }
-    tcg_temp_free_i64(tcg_tmp);
 
-    if (cond < 0x0e) { /* continue */
-        gen_set_label(label_continue);
+    /* If COND was false, force the flags to #nzcv.
+       Note that T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).  */
+    tcg_t2 = tcg_temp_new_i64();
+    tcg_gen_neg_i64(tcg_t1, tcg_t0);
+    tcg_gen_subi_i64(tcg_t2, tcg_t0, 1);
+
+    if (nzcv & 8) { /* N */
+        tcg_gen_or_i64(cpu_NF, cpu_NF, tcg_t1);
+    } else {
+        tcg_gen_and_i64(cpu_NF, cpu_NF, tcg_t2);
+    }
+    if (nzcv & 4) { /* Z */
+        tcg_gen_and_i64(cpu_ZF, cpu_ZF, tcg_t2);
+    } else {
+        tcg_gen_or_i64(cpu_ZF, cpu_ZF, tcg_t0);
+    }
+    if (nzcv & 2) { /* C */
+        tcg_gen_or_i64(cpu_CF, cpu_CF, tcg_t0);
+    } else {
+        tcg_gen_and_i64(cpu_CF, cpu_CF, tcg_t2);
+    }
+    if (nzcv & 1) { /* V */
+        tcg_gen_or_i64(cpu_VF, cpu_VF, tcg_t1);
+    } else {
+        tcg_gen_and_i64(cpu_VF, cpu_VF, tcg_t2);
     }
+    tcg_temp_free_i64(tcg_t0);
+    tcg_temp_free_i64(tcg_t1);
+    tcg_temp_free_i64(tcg_t2);
 }
 
 /* C3.5.6 Conditional select
-- 
2.1.0

  parent reply	other threads:[~2015-02-19 21:15 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-02-19 21:14 [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 01/11] target-arm: Introduce DisasCompare Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits Richard Henderson
2015-03-10 16:08   ` Peter Maydell
2015-03-10 18:18     ` Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 03/11] target-arm: Handle always condition codes within arm_test_cc Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 04/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 05/11] target-arm: Recognize UXTB, UXTH, LSR, LSL Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 06/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 07/11] target-arm: Recognize ROR Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 08/11] target-arm: Use setcond and movcond for csel Richard Henderson
2015-02-19 21:14 ` Richard Henderson [this message]
2015-02-19 21:14 ` [Qemu-devel] [PATCH 10/11] target-arm: Implement fccmp branchless Richard Henderson
2015-02-20 13:57   ` Laurent Desnogues
2015-02-20 15:53     ` Richard Henderson
2015-02-23  7:43       ` Laurent Desnogues
2015-02-19 21:14 ` [Qemu-devel] [PATCH 11/11] target-arm: Implement fcsel with movcond Richard Henderson
2015-02-19 23:52 ` [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments Peter Maydell
2015-02-20 16:50   ` Alex Bennée
2015-02-20 17:50     ` Alex Bennée
2015-02-20 10:00 ` Laurent Desnogues
2015-02-20 10:54   ` Laurent Desnogues
2015-02-23  7:49 ` Laurent Desnogues

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