From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH 03/11] target-arm: Handle always condition codes within arm_test_cc
Date: Thu, 19 Feb 2015 13:14:21 -0800 [thread overview]
Message-ID: <1424380469-20138-4-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1424380469-20138-1-git-send-email-rth@twiddle.net>
Handling this with TCG_COND_ALWAYS will allow these unlikely
cases to be handled without special cases in the rest of the
translator. The TCG optimizer ought to be able to reduce
these ALWAYS conditions completely.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-arm/translate-a64.c | 9 +++++++++
target-arm/translate.c | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 763bf35..219e257 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1056,6 +1056,14 @@ static void arm_test_cc(DisasCompare *cmp, int cc)
tcg_gen_andc_i64(value, cpu_ZF, value);
break;
+ case 14: /* always */
+ case 15: /* always */
+ /* Use the ALWAYS condition, which will fold early.
+ It doesn't matter what we use for the value. */
+ cond = TCG_COND_ALWAYS;
+ value = cpu_ZF;
+ goto no_invert;
+
default:
fprintf(stderr, "Bad condition code 0x%x\n", cc);
abort();
@@ -1065,6 +1073,7 @@ static void arm_test_cc(DisasCompare *cmp, int cc)
cond = tcg_invert_cond(cond);
}
+ no_invert:
cmp->cond = cond;
cmp->value = value;
cmp->value_global = global;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 0d0a4d1..54edc33 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -816,6 +816,14 @@ static void arm_test_cc(DisasCompare *cmp, int cc)
tcg_gen_andc_i32(value, cpu_ZF, value);
break;
+ case 14: /* always */
+ case 15: /* always */
+ /* Use the ALWAYS condition, which will fold early.
+ It doesn't matter what we use for the value. */
+ cond = TCG_COND_ALWAYS;
+ value = cpu_ZF;
+ goto no_invert;
+
default:
fprintf(stderr, "Bad condition code 0x%x\n", cc);
abort();
@@ -825,6 +833,7 @@ static void arm_test_cc(DisasCompare *cmp, int cc)
cond = tcg_invert_cond(cond);
}
+ no_invert:
cmp->cond = cond;
cmp->value = value;
cmp->value_global = global;
--
2.1.0
next prev parent reply other threads:[~2015-02-19 21:15 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-19 21:14 [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 01/11] target-arm: Introduce DisasCompare Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits Richard Henderson
2015-03-10 16:08 ` Peter Maydell
2015-03-10 18:18 ` Richard Henderson
2015-02-19 21:14 ` Richard Henderson [this message]
2015-02-19 21:14 ` [Qemu-devel] [PATCH 04/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 05/11] target-arm: Recognize UXTB, UXTH, LSR, LSL Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 06/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 07/11] target-arm: Recognize ROR Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 08/11] target-arm: Use setcond and movcond for csel Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 09/11] target-arm: Implement ccmp branchless Richard Henderson
2015-02-19 21:14 ` [Qemu-devel] [PATCH 10/11] target-arm: Implement fccmp branchless Richard Henderson
2015-02-20 13:57 ` Laurent Desnogues
2015-02-20 15:53 ` Richard Henderson
2015-02-23 7:43 ` Laurent Desnogues
2015-02-19 21:14 ` [Qemu-devel] [PATCH 11/11] target-arm: Implement fcsel with movcond Richard Henderson
2015-02-19 23:52 ` [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments Peter Maydell
2015-02-20 16:50 ` Alex Bennée
2015-02-20 17:50 ` Alex Bennée
2015-02-20 10:00 ` Laurent Desnogues
2015-02-20 10:54 ` Laurent Desnogues
2015-02-23 7:49 ` Laurent Desnogues
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