From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53221) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YOYRL-0000db-KU for qemu-devel@nongnu.org; Thu, 19 Feb 2015 16:15:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YOYRF-0007LJ-KW for qemu-devel@nongnu.org; Thu, 19 Feb 2015 16:15:19 -0500 Received: from mail-qg0-x22d.google.com ([2607:f8b0:400d:c04::22d]:43277) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YOYRF-0007LE-Fr for qemu-devel@nongnu.org; Thu, 19 Feb 2015 16:15:13 -0500 Received: by mail-qg0-f45.google.com with SMTP id h3so9684783qgf.4 for ; Thu, 19 Feb 2015 13:15:13 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 19 Feb 2015 13:14:25 -0800 Message-Id: <1424380469-20138-8-git-send-email-rth@twiddle.net> In-Reply-To: <1424380469-20138-1-git-send-email-rth@twiddle.net> References: <1424380469-20138-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 07/11] target-arm: Recognize ROR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Signed-off-by: Richard Henderson --- target-arm/translate-a64.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ed97ed6..d139b2d 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3136,17 +3136,7 @@ static void disas_extract(DisasContext *s, uint32_t insn) tcg_rd = cpu_reg(s, rd); - if (imm) { - /* OPTME: we can special case rm==rn as a rotate */ - tcg_rm = read_cpu_reg(s, rm, sf); - tcg_rn = read_cpu_reg(s, rn, sf); - tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); - tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); - tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); - if (!sf) { - tcg_gen_ext32u_i64(tcg_rd, tcg_rd); - } - } else { + if (unlikely(imm == 0)) { /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, * so an extract from bit 0 is a special case. */ @@ -3155,8 +3145,27 @@ static void disas_extract(DisasContext *s, uint32_t insn) } else { tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); } + } else if (rm == rn) { /* ROR */ + tcg_rm = cpu_reg(s, rm); + if (sf) { + tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm); + } else { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(tmp, tcg_rm); + tcg_gen_rotri_i32(tmp, tmp, imm); + tcg_gen_extu_i32_i64(tcg_rd, tmp); + tcg_temp_free_i32(tmp); + } + } else { + tcg_rm = read_cpu_reg(s, rm, sf); + tcg_rn = read_cpu_reg(s, rn, sf); + tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); + tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); + tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); + if (!sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + } } - } } -- 2.1.0