From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQG-0002ZA-5Q for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YQeQF-0006us-GI for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:52 -0500 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:47158 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YQeQF-0006uk-BB for qemu-devel@nongnu.org; Wed, 25 Feb 2015 11:02:51 -0500 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Wed, 25 Feb 2015 16:02:39 +0000 Message-Id: <1424880159-29348-8-git-send-email-alex.bennee@linaro.org> In-Reply-To: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> References: <1424880159-29348-1-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 6/6] target-arm/cpu.h: document why env->spsr exists List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org I was getting very confused about the duplication of state. Perhaps we should just get rid of env->spsr and use helpers that understand the banking? Signed-off-by: Alex Bennée diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 11845a6..d7fd13f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -155,6 +155,11 @@ typedef struct CPUARMState { This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ uint32_t uncached_cpsr; + /* The spsr is a alias for spsr_elN where N is the current + * exception level. It is provided for here so the TCG msr/mrs + * implementation can access one register. Care needs to be taken + * to ensure the banked_spsr[] is also updated. + */ uint32_t spsr; /* Banked registers. */ -- 2.3.0