From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YRPXp-0001oy-Mm for qemu-devel@nongnu.org; Fri, 27 Feb 2015 13:21:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YRPXj-0002Or-9e for qemu-devel@nongnu.org; Fri, 27 Feb 2015 13:21:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42917) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YRPXj-0002Oe-1Q for qemu-devel@nongnu.org; Fri, 27 Feb 2015 13:21:43 -0500 From: Stefan Hajnoczi Date: Fri, 27 Feb 2015 18:19:06 +0000 Message-Id: <1425061147-1411-69-git-send-email-stefanha@redhat.com> In-Reply-To: <1425061147-1411-1-git-send-email-stefanha@redhat.com> References: <1425061147-1411-1-git-send-email-stefanha@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 68/69] libqos: Solve bug in interrupt checking when using MSIX in virtio-pci.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Marc=20Mar=C3=AD?= , Peter Maydell , Stefan Hajnoczi From: Marc Mar=C3=AD The MSIX interrupt was always acked without checking its value, which cau= sed a race condition. If the ISR was raised between the read and the acking, th= e ISR was never detected and it timed out. Signed-off-by: Marc Mar=C3=AD Reviewed-by: John Snow Tested-by: John Snow Message-id: 1424795655-16952-1-git-send-email-marc.mari.barcelo@gmail.com Signed-off-by: Stefan Hajnoczi --- tests/libqos/virtio-pci.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index 046a316..f9fb924 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -142,8 +142,12 @@ static bool qvirtio_pci_get_queue_isr_status(QVirtio= Device *d, QVirtQueue *vq) return qpci_msix_pending(dev->pdev, vqpci->msix_entry); } else { data =3D readl(vqpci->msix_addr); - writel(vqpci->msix_addr, 0); - return data =3D=3D vqpci->msix_data; + if (data =3D=3D vqpci->msix_data) { + writel(vqpci->msix_addr, 0); + return true; + } else { + return false; + } } } else { return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STAT= US) & 1; @@ -162,8 +166,12 @@ static bool qvirtio_pci_get_config_isr_status(QVirti= oDevice *d) return qpci_msix_pending(dev->pdev, dev->config_msix_entry); } else { data =3D readl(dev->config_msix_addr); - writel(dev->config_msix_addr, 0); - return data =3D=3D dev->config_msix_data; + if (data =3D=3D dev->config_msix_data) { + writel(dev->config_msix_addr, 0); + return true; + } else { + return false; + } } } else { return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STAT= US) & 2; --=20 2.1.0