From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVMAX-0006bT-0Y for qemu-devel@nongnu.org; Tue, 10 Mar 2015 11:34:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YVMAS-0008UF-SB for qemu-devel@nongnu.org; Tue, 10 Mar 2015 11:34:04 -0400 From: Marcel Apfelbaum Date: Tue, 10 Mar 2015 17:31:59 +0200 Message-Id: <1426001534-7151-14-git-send-email-marcel@redhat.com> In-Reply-To: <1426001534-7151-1-git-send-email-marcel@redhat.com> References: <1426001534-7151-1-git-send-email-marcel@redhat.com> Subject: [Qemu-devel] [PATCH v5 for-2.3 13/28] hw/acpi: remove from root bus 0 the crs resources used by other busses. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: seabios@seabios.org, kraxel@redhat.com, mst@redhat.com, quintela@redhat.com, agraf@suse.de, marcel@redhat.com, alex.williamson@redhat.com, kevin@koconnor.net, qemu-ppc@nongnu.org, hare@suse.de, imammedo@redhat.com, amit.shah@redhat.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net If multiple root busses are used, root bus 0 cannot use all the pci holes ranges. Remove the IO/mem ranges used by the other primary busses. Signed-off-by: Marcel Apfelbaum --- hw/i386/acpi-build.c | 84 ++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 72 insertions(+), 12 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 5a00f14..28d7a43 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -872,6 +872,9 @@ build_ssdt(GArray *table_data, GArray *linker, Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx; CrsRangeQ io_ranges = QLIST_HEAD_INITIALIZER(io_ranges); CrsRangeQ mem_ranges = QLIST_HEAD_INITIALIZER(mem_ranges); + uint64_t range_base, range_limit; + CrsRangeEntry *entry; + int root_bus_limit = 0xFF; int i; ssdt = init_aml_allocator(); @@ -900,6 +903,10 @@ build_ssdt(GArray *table_data, GArray *linker, continue; } + if (bus_info->bus < root_bus_limit) { + root_bus_limit = bus_info->bus - 1; + } + scope = aml_scope("\\_SB"); dev = aml_device("PC%.02X", (uint8_t)bus_info->bus); aml_append(dev, aml_name_decl("_UID", @@ -914,8 +921,6 @@ build_ssdt(GArray *table_data, GArray *linker, aml_append(ssdt, scope); } - crs_range_list_free(&io_ranges); - crs_range_list_free(&mem_ranges); qapi_free_PciInfoList(info_list); } @@ -924,26 +929,78 @@ build_ssdt(GArray *table_data, GArray *linker, crs = aml_resource_template(); aml_append(crs, aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode, - 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100)); + 0x0000, 0x0, root_bus_limit, + 0x0000, root_bus_limit + 1)); aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)); aml_append(crs, aml_word_io(aml_min_fixed, aml_max_fixed, aml_pos_decode, aml_entire_range, 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); - aml_append(crs, - aml_word_io(aml_min_fixed, aml_max_fixed, - aml_pos_decode, aml_entire_range, - 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300)); + + /* prepare PCI IO ranges */ + range_base = 0x0D00; + range_limit = 0xFFFF; + if (QLIST_EMPTY(&io_ranges)) { + aml_append(crs, + aml_word_io(aml_min_fixed, aml_max_fixed, + aml_pos_decode, aml_entire_range, + 0x0000, range_base, range_limit, + 0x0000, range_limit - range_base + 1)); + } else { + QLIST_FOREACH(entry, &io_ranges, entry) { + if (range_base < entry->base) { + aml_append(crs, + aml_word_io(aml_min_fixed, aml_max_fixed, + aml_pos_decode, aml_entire_range, + 0x0000, range_base, entry->base - 1, + 0x0000, entry->base - range_base)); + } + range_base = entry->limit + 1; + if (!QLIST_NEXT(entry, entry)) { + aml_append(crs, + aml_word_io(aml_min_fixed, aml_max_fixed, + aml_pos_decode, aml_entire_range, + 0x0000, range_base, range_limit, + 0x0000, range_limit - range_base + 1)); + } + } + } + aml_append(crs, aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, aml_cacheable, aml_ReadWrite, 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); - aml_append(crs, - aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, - aml_non_cacheable, aml_ReadWrite, - 0, pci->w32.begin, pci->w32.end - 1, 0, - pci->w32.end - pci->w32.begin)); + + /* prepare PCI memory ranges */ + range_base = pci->w32.begin; + range_limit = pci->w32.end - 1; + if (QLIST_EMPTY(&mem_ranges)) { + aml_append(crs, + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, + aml_non_cacheable, aml_ReadWrite, + 0, range_base, range_limit, + 0, range_limit - range_base + 1)); + } else { + QLIST_FOREACH(entry, &mem_ranges, entry) { + if (range_base < entry->base) { + aml_append(crs, + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, + aml_non_cacheable, aml_ReadWrite, + 0, range_base, entry->base - 1, + 0, entry->base - range_base)); + } + range_base = entry->limit + 1; + if (!QLIST_NEXT(entry, entry)) { + aml_append(crs, + aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, + aml_non_cacheable, aml_ReadWrite, + 0, range_base, range_limit, + 0, range_base - range_limit + 1)); + } + } + } + if (pci->w64.begin) { aml_append(crs, aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed, @@ -966,6 +1023,9 @@ build_ssdt(GArray *table_data, GArray *linker, aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); + crs_range_list_free(&io_ranges); + crs_range_list_free(&mem_ranges); + /* reserve PCIHP resources */ if (pm->pcihp_io_len) { dev = aml_device("PHPR"); -- 2.1.0