From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60274) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YWWKo-0005TF-GL for qemu-devel@nongnu.org; Fri, 13 Mar 2015 16:37:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YWW7h-0003EW-VJ for qemu-devel@nongnu.org; Fri, 13 Mar 2015 16:24:07 -0400 Received: from mail-qc0-x236.google.com ([2607:f8b0:400d:c01::236]:38154) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YWW7h-0003EQ-Qv for qemu-devel@nongnu.org; Fri, 13 Mar 2015 16:23:57 -0400 Received: by qcvp6 with SMTP id p6so29496165qcv.5 for ; Fri, 13 Mar 2015 13:23:57 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 13 Mar 2015 13:23:13 -0700 Message-Id: <1426278193-15317-7-git-send-email-rth@twiddle.net> In-Reply-To: <1426278193-15317-1-git-send-email-rth@twiddle.net> References: <1426278193-15317-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 6/6] tcg: Complete handling of ALWAYS and NEVER List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Missing from movcond, and brcondi_i32 (but not brcondi_i64). Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 6674bb4..f7a2767 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -286,9 +286,13 @@ void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l) void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l) { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_brcond_i32(cond, arg1, t0, l); - tcg_temp_free_i32(t0); + if (cond == TCG_COND_ALWAYS) { + tcg_gen_br(l); + } else if (cond != TCG_COND_NEVER) { + TCGv_i32 t0 = tcg_const_i32(arg2); + tcg_gen_brcond_i32(cond, arg1, t0, l); + tcg_temp_free_i32(t0); + } } void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, @@ -546,7 +550,11 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) { - if (TCG_TARGET_HAS_movcond_i32) { + if (cond == TCG_COND_ALWAYS) { + tcg_gen_mov_i32(ret, v1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_mov_i32(ret, v2); + } else if (TCG_TARGET_HAS_movcond_i32) { tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond); } else { TCGv_i32 t0 = tcg_temp_new_i32(); @@ -1590,7 +1598,11 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) { - if (TCG_TARGET_REG_BITS == 32) { + if (cond == TCG_COND_ALWAYS) { + tcg_gen_mov_i64(ret, v1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_mov_i64(ret, v2); + } else if (TCG_TARGET_REG_BITS == 32) { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, -- 2.1.0