From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXWWR-0002yB-Cn for qemu-devel@nongnu.org; Mon, 16 Mar 2015 11:01:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YXWWN-0004Zu-DT for qemu-devel@nongnu.org; Mon, 16 Mar 2015 11:01:39 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:58903) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXWWN-0004Z9-89 for qemu-devel@nongnu.org; Mon, 16 Mar 2015 11:01:35 -0400 From: Bastian Koppelmann Date: Mon, 16 Mar 2015 16:02:54 +0000 Message-Id: <1426521780-31653-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 0/6] tricore patches for 2.3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Hi Peter, here are my last tricore patches for this release, which finish up all the integer instructions (with the exception of trap related instructions). I hope it's okay if I squeeze them into this release. Cheers, Bastian The following changes since commit 307146cb9359ad6d4544e00af073088772d165eb: Merge remote-tracking branch 'remotes/kvaneesh/for-upstream' into staging (2015-03-16 13:04:09 +0000) are available in the git repository at: https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150316 for you to fetch changes up to b724b012a4ea9877c5ddad254df63735a945618c: target-tricore: Add instructions of SYS opcode format (2015-03-16 15:53:08 +0000) ---------------------------------------------------------------- TriCore RRR1, RRRR, RRRW, and SYS instructions ---------------------------------------------------------------- Bastian Koppelmann (6): target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as first opcode target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as first opcode target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode target-tricore: Add instructions of RRRR opcode format target-tricore: Add instructions of RRRW opcode format target-tricore: Add instructions of SYS opcode format target-tricore/cpu.h | 7 + target-tricore/helper.h | 12 + target-tricore/op_helper.c | 436 +++ target-tricore/translate.c | 6767 +++++++++++++++++++++++--------------- target-tricore/tricore-opcodes.h | 56 +- 5 files changed, 4526 insertions(+), 2752 deletions(-) -- 2.3.3