From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXtUz-0000MV-SI for qemu-devel@nongnu.org; Tue, 17 Mar 2015 11:33:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YXtUw-0004pH-Kv for qemu-devel@nongnu.org; Tue, 17 Mar 2015 11:33:41 -0400 Received: from mail-lb0-x231.google.com ([2a00:1450:4010:c04::231]:33939) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXtUw-0004op-EK for qemu-devel@nongnu.org; Tue, 17 Mar 2015 11:33:38 -0400 Received: by lbbsy1 with SMTP id sy1so9824032lbb.1 for ; Tue, 17 Mar 2015 08:33:36 -0700 (PDT) From: Sergey Fedorov Date: Tue, 17 Mar 2015 18:33:02 +0300 Message-Id: <1426606382-15345-1-git-send-email-serge.fdrv@gmail.com> Subject: [Qemu-devel] [PATCH] target-arm: rename c1_coproc to cpacr_el1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Sergey Fedorov , Peter Maydell Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Signed-off-by: Sergey Fedorov --- hw/arm/pxa2xx.c | 2 +- target-arm/cpu.h | 4 ++-- target-arm/helper.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 165ba2a..f921a56 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -274,7 +274,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; s->cpu->env.cp15.sctlr_ns = 0; - s->cpu->env.cp15.c1_coproc = 0; + s->cpu->env.cp15.cpacr_el1 = 0; s->cpu->env.cp15.ttbr0_el[1] = 0; s->cpu->env.cp15.dacr_ns = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 083211c..d63d9b2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -201,7 +201,7 @@ typedef struct CPUARMState { }; uint64_t sctlr_el[4]; }; - uint64_t c1_coproc; /* Coprocessor access register. */ + uint64_t cpacr_el1; /* Architectural feature access control register */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ @@ -1813,7 +1813,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, int fpen; if (arm_feature(env, ARM_FEATURE_V6)) { - fpen = extract32(env->cp15.c1_coproc, 20, 2); + fpen = extract32(env->cp15.cpacr_el1, 20, 2); } else { /* CPACR doesn't exist before v6, so VFP is always accessible */ fpen = 3; diff --git a/target-arm/helper.c b/target-arm/helper.c index 10886c5..7c54dcf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -589,7 +589,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, } value &= mask; } - env->cp15.c1_coproc = value; + env->cp15.cpacr_el1 = value; } static const ARMCPRegInfo v6_cp_reginfo[] = { @@ -615,7 +615,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), .resetvalue = 0, .writefn = cpacr_write }, REGINFO_SENTINEL }; -- 2.3.1