From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YY4PJ-0008Oa-BX for qemu-devel@nongnu.org; Tue, 17 Mar 2015 23:12:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YY4PE-0002BQ-3i for qemu-devel@nongnu.org; Tue, 17 Mar 2015 23:12:33 -0400 Received: from e23smtp04.au.ibm.com ([202.81.31.146]:56081) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YY4PD-0002AZ-HU for qemu-devel@nongnu.org; Tue, 17 Mar 2015 23:12:28 -0400 Received: from /spool/local by e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 18 Mar 2015 13:12:24 +1000 From: Alexey Kardashevskiy Date: Wed, 18 Mar 2015 14:11:21 +1100 Message-Id: <1426648281-13955-1-git-send-email-aik@ozlabs.ru> Subject: [Qemu-devel] [PATCH qemu] target-ppc: Remove never existed POWER5+ v0.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexey Kardashevskiy , qemu-ppc@nongnu.org, Alexander Graf , =?UTF-8?q?Andreas=20F=C3=A4rber?= IBM uses low 16bits to specify a chip version of a POWER CPU. So there has never been an actual silicon with PVR = 0x003B0000. The first silicon would have PVR 0x003B0100 but it is very unlikely to find it in any machine shipped to any customer as it is was too raw. This removes CPU_POWERPC_POWER5P_v00 definition and changes POWER5+ and POWERgs aliases (which are synonyms) to point to POWER5+_v2.1 which can still be found in real machines. Signed-off-by: Alexey Kardashevskiy --- I asked Paul. He suggested that there has never been an actual POWER5 silicon with PVR which low 16 bits are zeroes, the first one would be 0x003B0100 but it would be so buggy so it would not be shipped to any real customer. And then he suggested to look at the real POWER5+ machine, we looked around and found one: cpu : POWER5+ (gs) clock : 1898.100000MHz revision : 2.0 (pvr 003b 0200) I believe 3b 0201 is also something real and it is defined already in QEMU so here is a patch. Yes, this does not touch the cpu family class registration issue, just a tiny cleanup :) --- target-ppc/cpu-models.c | 6 ++---- target-ppc/cpu-models.h | 1 - 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index 2b560a4..4d5ab4b 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -1124,8 +1124,6 @@ POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5, "POWER5") #endif - POWERPC_DEF("POWER5+_v0.0", CPU_POWERPC_POWER5P_v00, POWER5P, - "POWER5+ v0.0") POWERPC_DEF("POWER5+_v2.1", CPU_POWERPC_POWER5P_v21, POWER5P, "POWER5+ v2.1") #if defined(TODO) @@ -1387,8 +1385,8 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { { "Dino", "POWER3" }, { "POWER3+", "631" }, { "POWER5gr", "POWER5" }, - { "POWER5+", "POWER5+_v0.0" }, - { "POWER5gs", "POWER5+_v0.0" }, + { "POWER5+", "POWER5+_v2.1" }, + { "POWER5gs", "POWER5+_v2.1" }, { "POWER7", "POWER7_v2.3" }, { "POWER7+", "POWER7+_v2.1" }, { "POWER8E", "POWER8E_v1.0" }, diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h index ee693af..9d80e72 100644 --- a/target-ppc/cpu-models.h +++ b/target-ppc/cpu-models.h @@ -547,7 +547,6 @@ enum { CPU_POWERPC_POWER4P = 0x00380000, /* XXX: missing 0x003A0201 */ CPU_POWERPC_POWER5 = 0x003A0203, - CPU_POWERPC_POWER5P_v00 = 0x003B0000, CPU_POWERPC_POWER5P_v21 = 0x003B0201, CPU_POWERPC_POWER6 = 0x003E0000, CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */ -- 2.0.0