* [Qemu-devel] [PULL 1/2] Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell"
2015-03-19 19:40 [Qemu-devel] [PULL 0/2] X86 queue 2015-03-19 Eduardo Habkost
@ 2015-03-19 19:40 ` Eduardo Habkost
2015-03-19 19:40 ` [Qemu-devel] [PULL 2/2] target-i386: Haswell-noTSX and Broadwell-noTSX Eduardo Habkost
2015-03-20 13:18 ` [Qemu-devel] [PULL 0/2] X86 queue 2015-03-19 Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Eduardo Habkost @ 2015-03-19 19:40 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Paolo Bonzini, Igor Mammedov, Jiri Denemark,
Andreas Färber
This reverts commit 13704e4c455770d500d6b87b117e32f0d01252c9.
With the Intel microcode update that removed HLE and RTM, there will be
different kinds of Haswell and Broadwell CPUs out there: some that still
have the HLE and RTM features, and some that don't have the HLE and RTM
features. On both cases people may be willing to use the pc-*-2.3
machine-types.
So instead of making the CPU model results confusing by making it depend
on the machine-type, keep HLE and RTM on the existing Haswell and
Broadwell CPU models. The plan is to introduce "Haswell-noTSX" and
"Broadwell-noTSX" CPU models later, for people who have CPUs that don't
have TSX feature available.
Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
hw/i386/pc_piix.c | 4 ----
hw/i386/pc_q35.c | 4 ----
target-i386/cpu.c | 9 +++++----
3 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 36c69d7..1fe7bfb 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -331,10 +331,6 @@ static void pc_compat_2_2(MachineState *machine)
x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
- x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
- x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
machine->suppress_vmdesc = true;
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index bc40537..dcc17c0 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -310,10 +310,6 @@ static void pc_compat_2_2(MachineState *machine)
x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
- x86_cpu_compat_set_features("Haswell", FEAT_7_0_EBX,
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
- x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_RTM, 0);
machine->suppress_vmdesc = true;
}
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index f01690b..02def07 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1099,8 +1099,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+ CPUID_7_0_EBX_RTM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
.xlevel = 0x8000000A,
@@ -1133,9 +1134,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
--
2.1.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [Qemu-devel] [PULL 2/2] target-i386: Haswell-noTSX and Broadwell-noTSX
2015-03-19 19:40 [Qemu-devel] [PULL 0/2] X86 queue 2015-03-19 Eduardo Habkost
2015-03-19 19:40 ` [Qemu-devel] [PULL 1/2] Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell" Eduardo Habkost
@ 2015-03-19 19:40 ` Eduardo Habkost
2015-03-20 13:18 ` [Qemu-devel] [PULL 0/2] X86 queue 2015-03-19 Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Eduardo Habkost @ 2015-03-19 19:40 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Paolo Bonzini, Igor Mammedov, Jiri Denemark,
Andreas Färber
With the Intel microcode update that removed HLE and RTM, there will be
different kinds of Haswell and Broadwell CPUs out there: some that still
have the HLE and RTM features, and some that don't have the HLE and RTM
features. On both cases people may be willing to use the pc-*-2.3
machine-types.
So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU
models, for hosts that have Haswell and Broadwell CPUs without TSX support.
Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/cpu.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 02def07..b2d1c95 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1073,6 +1073,39 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
},
{
+ .name = "Haswell-noTSX",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 60,
+ .stepping = 1,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+ CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Core Processor (Haswell, no TSX)",
+ }, {
.name = "Haswell",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
@@ -1108,6 +1141,42 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Intel Core Processor (Haswell)",
},
{
+ .name = "Broadwell-noTSX",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 61,
+ .stepping = 2,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+ CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+ CPUID_7_0_EBX_SMAP,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Core Processor (Broadwell, no TSX)",
+ },
+ {
.name = "Broadwell",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
--
2.1.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [Qemu-devel] [PULL 0/2] X86 queue 2015-03-19
2015-03-19 19:40 [Qemu-devel] [PULL 0/2] X86 queue 2015-03-19 Eduardo Habkost
2015-03-19 19:40 ` [Qemu-devel] [PULL 1/2] Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell" Eduardo Habkost
2015-03-19 19:40 ` [Qemu-devel] [PULL 2/2] target-i386: Haswell-noTSX and Broadwell-noTSX Eduardo Habkost
@ 2015-03-20 13:18 ` Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2015-03-20 13:18 UTC (permalink / raw)
To: Eduardo Habkost
Cc: QEMU Developers, Paolo Bonzini, Igor Mammedov, Jiri Denemark,
Andreas Färber
On 19 March 2015 at 19:40, Eduardo Habkost <ehabkost@redhat.com> wrote:
> The following changes since commit 3e5f6234b4f45a11b7c357dde2d6da36641bc6f6:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2015-03-19 17:47:08 +0000)
>
> are available in the git repository at:
>
> https://github.com/ehabkost/qemu.git tags/x86-pull-request
>
> for you to fetch changes up to a356850b80b3d13b2ef737dad2acb05e6da03753:
>
> target-i386: Haswell-noTSX and Broadwell-noTSX (2015-03-19 16:35:14 -0300)
>
> ----------------------------------------------------------------
> X86 queue 2015-03-19
>
> ----------------------------------------------------------------
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread