From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 2/4] target-tricore: fix DVINIT_HU/BU calculating overflow before result
Date: Tue, 24 Mar 2015 09:58:17 +0100 [thread overview]
Message-ID: <1427187499-28387-3-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1427187499-28387-1-git-send-email-kbastian@mail.uni-paderborn.de>
dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is needed
for the overflow bits, after calculating the overflow bits.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 30 ++++++++++++++++++------------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 0b7cf06..989a047 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6240,7 +6240,7 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
uint32_t op2;
int r1, r2, r3;
- TCGv temp, temp2;
+ TCGv temp, temp2, temp3;
op2 = MASK_OP_RR_OP2(ctx->opcode);
r3 = MASK_OP_RR_D(ctx->opcode);
@@ -6261,14 +6261,17 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RR_DVINIT_BU:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
+ temp3 = tcg_temp_new();
+
+ tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
+ tcg_gen_neg_tl(temp, temp3);
/* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
- temp, cpu_gpr_d[r3+1]);
+ tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
+ temp, temp3);
tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
temp2, cpu_gpr_d[r2]);
@@ -6281,12 +6284,12 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
/* sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
- tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 8);
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
- tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp);
+ tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
+ tcg_temp_free(temp3);
break;
case OPC2_32_RR_DVINIT_H:
gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
@@ -6295,14 +6298,17 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
case OPC2_32_RR_DVINIT_HU:
temp = tcg_temp_new();
temp2 = tcg_temp_new();
+ temp3 = tcg_temp_new();
+
+ tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
/* reset av */
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
+ tcg_gen_neg_tl(temp, temp3);
/* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
- temp, cpu_gpr_d[r3+1]);
+ tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
+ temp, temp3);
tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
temp2, cpu_gpr_d[r2]);
@@ -6315,11 +6321,11 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
/* sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
- tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
- tcg_gen_shri_tl(cpu_gpr_d[r3+1], temp, 16);
- tcg_gen_shli_tl(cpu_gpr_d[r3], temp, 16);
+ tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
+ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
tcg_temp_free(temp);
tcg_temp_free(temp2);
+ tcg_temp_free(temp3);
break;
case OPC2_32_RR_DVINIT:
temp = tcg_temp_new();
--
2.3.3
next prev parent reply other threads:[~2015-03-24 8:58 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-24 8:58 [Qemu-devel] [PULL 0/4] tricore-patches for 2.3-rc1 Bastian Koppelmann
2015-03-24 8:58 ` [Qemu-devel] [PULL 1/4] target-tricore: Fix two helper functions (clang warnings) Bastian Koppelmann
2015-03-24 8:58 ` Bastian Koppelmann [this message]
2015-03-24 8:58 ` [Qemu-devel] [PULL 3/4] target-tricore: fix RRPW_DEXTR using wrong reg Bastian Koppelmann
2015-03-24 8:58 ` [Qemu-devel] [PULL 4/4] target-tricore: properly fix dvinit_b/h_13 Bastian Koppelmann
2015-03-24 11:12 ` [Qemu-devel] [PULL 0/4] tricore-patches for 2.3-rc1 Peter Maydell
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