From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YcY9z-0000KH-CN for qemu-devel@nongnu.org; Mon, 30 Mar 2015 07:47:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YcY9m-0002Ao-0W for qemu-devel@nongnu.org; Mon, 30 Mar 2015 07:47:15 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:55872) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YcY9l-0002A7-Hk for qemu-devel@nongnu.org; Mon, 30 Mar 2015 07:47:01 -0400 From: Bastian Koppelmann Date: Mon, 30 Mar 2015 13:46:49 +0200 Message-Id: <1427716009-15564-2-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1427716009-15564-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1427716009-15564-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL] target-tricore: fix CACHEA/I_POSTINC/PREINC using data register.. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org ..for address calculation instead address registers. Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index bbcfee9..54a48cd 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -4509,14 +4509,14 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, case OPC2_32_BO_CACHEA_I_POSTINC: /* instruction to access the cache, but we still need to handle the addressing mode */ - tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); break; case OPC2_32_BO_CACHEA_WI_PREINC: case OPC2_32_BO_CACHEA_W_PREINC: case OPC2_32_BO_CACHEA_I_PREINC: /* instruction to access the cache, but we still need to handle the addressing mode */ - tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); break; case OPC2_32_BO_CACHEI_WI_SHORTOFF: case OPC2_32_BO_CACHEI_W_SHORTOFF: @@ -4526,13 +4526,13 @@ static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, case OPC2_32_BO_CACHEI_W_POSTINC: case OPC2_32_BO_CACHEI_WI_POSTINC: if (tricore_feature(env, TRICORE_FEATURE_131)) { - tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); } /* TODO: else raise illegal opcode trap */ break; case OPC2_32_BO_CACHEI_W_PREINC: case OPC2_32_BO_CACHEI_WI_PREINC: if (tricore_feature(env, TRICORE_FEATURE_131)) { - tcg_gen_addi_tl(cpu_gpr_d[r2], cpu_gpr_d[r2], off10); + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); } /* TODO: else raise illegal opcode trap */ break; case OPC2_32_BO_ST_A_SHORTOFF: -- 2.3.4