From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47797) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ydg0A-0004Er-On for qemu-devel@nongnu.org; Thu, 02 Apr 2015 10:21:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ydg05-0002vs-Uo for qemu-devel@nongnu.org; Thu, 02 Apr 2015 10:21:46 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46766) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ydg05-0002vi-Q0 for qemu-devel@nongnu.org; Thu, 02 Apr 2015 10:21:41 -0400 From: Paolo Bonzini Date: Thu, 2 Apr 2015 16:21:28 +0200 Message-Id: <1427984491-23475-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1427984491-23475-1-git-send-email-pbonzini@redhat.com> References: <1427984491-23475-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 3/6] target-i386: clear bsp bit when designating bsp List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Nadav Amit From: Nadav Amit Since the BSP bit is writable on real hardware, during reset all the CPUs which were not chosen to be the BSP should have their BSP bit cleared. This fix is required for KVM to work correctly when it changes the BSP bit. An additional fix is required for QEMU tcg to allow software to change the BSP bit. Signed-off-by: Nadav Amit Message-Id: <1427932716-11800-1-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini --- hw/intc/apic_common.c | 8 ++++++-- include/hw/i386/apic.h | 2 +- target-i386/cpu.c | 4 +--- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 0858b45..042e960 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -215,14 +215,18 @@ void apic_init_reset(DeviceState *dev) } } -void apic_designate_bsp(DeviceState *dev) +void apic_designate_bsp(DeviceState *dev, bool bsp) { if (dev == NULL) { return; } APICCommonState *s = APIC_COMMON(dev); - s->apicbase |= MSR_IA32_APICBASE_BSP; + if (bsp) { + s->apicbase |= MSR_IA32_APICBASE_BSP; + } else { + s->apicbase &= ~MSR_IA32_APICBASE_BSP; + } } static void apic_reset_common(DeviceState *dev) diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index 1d48e02..51eb6d3 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -21,7 +21,7 @@ void apic_sipi(DeviceState *s); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, TPRAccess access); void apic_poll_irq(DeviceState *d); -void apic_designate_bsp(DeviceState *d); +void apic_designate_bsp(DeviceState *d, bool bsp); /* pc.c */ DeviceState *cpu_get_current_apic(void); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b2d1c95..03b33cf 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2714,9 +2714,7 @@ static void x86_cpu_reset(CPUState *s) #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ - if (s->cpu_index == 0) { - apic_designate_bsp(cpu->apic_state); - } + apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); s->halted = !cpu_is_bsp(cpu); -- 2.3.4