From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Greg Bellows" <greg.bellows@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 00/14] Add memory attributes and use them in ARM
Date: Tue, 7 Apr 2015 21:09:46 +0100 [thread overview]
Message-ID: <1428437400-8474-1-git-send-email-peter.maydell@linaro.org> (raw)
Following from my previous RFC about transaction memory attributes,
here's some code I think is good enough to drop the 'RFC' tag :-)
(read: I would like to land this when master reopens for 2.4.)
I've included both the changes to the core memory system code
and the target-arm changes as a usage example, but the ARM stuff
is all at the end of the series, so if we want to split it and
take it via separate subtrees that's fine.
I think I have followed the outcome of our discussions on the
RFC; please let me know if I got confused or missed something.
What we have here is:
* MemoryRegions can provide read_with_attrs and write_with_attrs
so they can get memory attributes and return a success/error
indication
* the attributes and error indication are plumbed through the
core memory system code
* new functions address_space_ld*/st* are provided which are
like the old ld/st*_phys but have extra args for MemTxAttrs
and MemTxResult*
* callers have been auto-converted from the old ld/st*_phys
unless they were using the CPUState::as address space
[those will be moved to some cpu-specific API later]
* TCG frontends can use tlb_set_page_with_attrs() to provide
attributes when they add an entry to the TLB
* two attributes: MEMTXATTRS_SECURE [ARM TrustZone secure access]
and MEMTXATTRS_USER [access is unprivileged], both implemented
for the ARM CPU frontend (these both correspond to AMBA/AXI
bus sideband signals, more or less)
I believe this code contains enough changes that all the memory
transactions issued by the ARM CPU will correctly be marked as
S or NS. Obviously nothing currently pays attention to this, but
the patches to make the GIC model support TrustZone can be easily
wired up to this.
The diffstat's quite big but the biggest patch is a Coccinelle
generated automated rename of the callers of ld/st*_phys to
address_space_ld/st* where they don't use the CPUState::as.
thanks
-- PMM
Peter Maydell (14):
memory: Define API for MemoryRegionOps to take attrs and return status
memory: Add MemTxAttrs, MemTxResult to io_mem_read and io_mem_write
Make CPU iotlb a structure rather than a plain hwaddr
Add MemTxAttrs to the IOTLB
exec.c: Convert subpage memory ops to _with_attrs
exec.c: Make address_space_rw take transaction attributes
exec.c: Add new address_space_ld*/st* functions
Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
exec.c: Capture the memory attributes for a watchpoint hit
target-arm: Honour NS bits in page tables
target-arm: Use correct memory attributes for page table walks
target-arm: Add user-mode transaction attribute
target-arm: Use attribute info to handle user-only watchpoints
target-arm: Check watchpoints against CPU security state
cputlb.c | 22 +-
dma-helpers.c | 3 +-
exec.c | 418 +++++++++++++++++++++++++++++---------
hw/alpha/dp264.c | 9 +-
hw/alpha/typhoon.c | 3 +-
hw/arm/boot.c | 6 +-
hw/arm/highbank.c | 12 +-
hw/dma/pl080.c | 20 +-
hw/dma/sun4m_iommu.c | 3 +-
hw/i386/intel_iommu.c | 3 +-
hw/mips/mips_jazz.c | 6 +-
hw/pci-host/apb.c | 3 +-
hw/pci-host/prep.c | 6 +-
hw/pci/msi.c | 3 +-
hw/pci/msix.c | 3 +-
hw/s390x/css.c | 19 +-
hw/s390x/s390-pci-bus.c | 9 +-
hw/s390x/s390-pci-inst.c | 7 +-
hw/s390x/s390-virtio-bus.c | 73 ++++---
hw/s390x/s390-virtio.c | 4 +-
hw/s390x/virtio-ccw.c | 87 +++++---
hw/sh4/r2d.c | 6 +-
hw/timer/hpet.c | 5 +-
hw/vfio/pci.c | 4 +-
include/exec/cpu-defs.h | 15 +-
include/exec/exec-all.h | 7 +-
include/exec/memattrs.h | 40 ++++
include/exec/memory.h | 128 +++++++++++-
include/qom/cpu.h | 2 +
include/sysemu/dma.h | 3 +-
ioport.c | 16 +-
kvm-all.c | 3 +-
memory.c | 212 ++++++++++++-------
monitor.c | 3 +-
scripts/coverity-model.c | 8 +-
softmmu_template.h | 36 ++--
target-arm/helper.c | 134 ++++++++++--
target-arm/op_helper.c | 29 +--
target-i386/arch_memory_mapping.c | 15 +-
39 files changed, 1038 insertions(+), 347 deletions(-)
create mode 100644 include/exec/memattrs.h
--
1.9.1
next reply other threads:[~2015-04-07 20:10 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-07 20:09 Peter Maydell [this message]
2015-04-07 20:09 ` [Qemu-devel] [PATCH 01/14] memory: Define API for MemoryRegionOps to take attrs and return status Peter Maydell
2015-04-08 10:49 ` Paolo Bonzini
2015-04-09 8:55 ` Edgar E. Iglesias
2015-04-09 9:04 ` Peter Maydell
2015-04-09 9:21 ` Paolo Bonzini
2015-04-10 2:07 ` Edgar E. Iglesias
2015-04-10 14:51 ` Peter Maydell
2015-04-11 10:27 ` Edgar E. Iglesias
2015-04-09 9:32 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 02/14] memory: Add MemTxAttrs, MemTxResult to io_mem_read and io_mem_write Peter Maydell
2015-04-08 10:51 ` Paolo Bonzini
2015-04-08 10:59 ` Peter Maydell
2015-04-08 11:13 ` Paolo Bonzini
2015-04-09 8:59 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 03/14] Make CPU iotlb a structure rather than a plain hwaddr Peter Maydell
2015-04-08 10:52 ` Paolo Bonzini
2015-04-09 9:02 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 04/14] Add MemTxAttrs to the IOTLB Peter Maydell
2015-04-08 10:53 ` Paolo Bonzini
2015-04-09 9:04 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 05/14] exec.c: Convert subpage memory ops to _with_attrs Peter Maydell
2015-04-08 10:54 ` Paolo Bonzini
2015-04-09 9:07 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 06/14] exec.c: Make address_space_rw take transaction attributes Peter Maydell
2015-04-08 12:55 ` Paolo Bonzini
2015-04-09 9:59 ` Edgar E. Iglesias
2015-04-09 10:14 ` Peter Maydell
2015-04-09 10:21 ` Paolo Bonzini
2015-04-09 10:43 ` Peter Maydell
2015-04-09 11:40 ` Paolo Bonzini
2015-04-09 11:43 ` Peter Maydell
2015-04-07 20:09 ` [Qemu-devel] [PATCH 07/14] exec.c: Add new address_space_ld*/st* functions Peter Maydell
2015-04-08 11:03 ` Paolo Bonzini
2015-04-09 11:49 ` Peter Maydell
2015-04-09 12:00 ` Paolo Bonzini
2015-04-09 12:38 ` Peter Maydell
2015-04-09 12:42 ` Paolo Bonzini
2015-04-09 10:34 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 08/14] Switch non-CPU callers from ld/st*_phys to address_space_ld/st* Peter Maydell
2015-04-09 10:44 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 09/14] exec.c: Capture the memory attributes for a watchpoint hit Peter Maydell
2015-04-08 11:04 ` Paolo Bonzini
2015-04-08 11:14 ` Peter Maydell
2015-04-07 20:09 ` [Qemu-devel] [PATCH 10/14] target-arm: Honour NS bits in page tables Peter Maydell
2015-04-09 11:23 ` Edgar E. Iglesias
2015-04-09 14:14 ` Peter Maydell
2015-04-09 14:23 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 11/14] target-arm: Use correct memory attributes for page table walks Peter Maydell
2015-04-09 11:34 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 12/14] target-arm: Add user-mode transaction attribute Peter Maydell
2015-04-07 20:09 ` [Qemu-devel] [PATCH 13/14] target-arm: Use attribute info to handle user-only watchpoints Peter Maydell
2015-04-09 11:37 ` Edgar E. Iglesias
2015-04-07 20:10 ` [Qemu-devel] [PATCH 14/14] target-arm: Check watchpoints against CPU security state Peter Maydell
2015-04-09 11:38 ` Edgar E. Iglesias
2015-04-09 9:37 ` [Qemu-devel] [PATCH 00/14] Add memory attributes and use them in ARM Edgar E. Iglesias
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